User-configurable on-chip program memory system

• US 6,321,318 B1
• Filed: 12/15/1998
• Issued: 11/20/2001
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Simar, Ray L. Jr., Baltz, Philip K.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US09/212,894
• Time in Patent Office: 1,071 Days
• Field of Search: 711/170, 711/100, 711/118
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory

Abstract

A processor structure and method of operation are disclosed that comprise a user-configurable on-chip program memory system. The memory system comprises an on-chip memory 31 and a program memory controller 30 that reconfigures memory 31 in response to control values that may be modified by CPU core 20 under program control. In one mode, memory 31 may be mapped into internal address space. In other modes, memory 31 may be configured as an on-chip cache. In conjunction with the cache configuration, the program memory controller may comprise a tag RAM that is initialized upon a transition to cache mode. Program memory controller 30 handles memory mode transitions and data requests; CPU core 20 preferably requests stored instructions from controller 30 in a uniform fashion regardless of memory mode.

Claims

1. A microprocessor comprising:

a central processing unit;

an on-chip memory array for storing instructions executable on said central processing unit;

an external memory interface capable of reading from and writing to an off-chip memory instructions executable on said central processing unit; and

a configurable program memory controller in communication with said central processing unit, said on-chip memory array, and said external memory interface, said configurable program memory controller having a plurality of operating modes, including a first mode in which it uses said on-chip memory array as a memory-mapped on-chip memory, and a second mode in which it uses said on-chip memory array as a cache on-chip memory, said configurable program memory controller operable to transition between said second mode to said first mode only following a cache miss.

2. The microprocessor of claim 1, further comprising:

a cache tag memory having a plurality of validity bits, each validity bit indicating a valid state or an invalid state for a corresponding portion of said on-chip memory array; and

wherein said configurable program memory controller is further operable to always reset all validity bits to indicate said invalid state upon each and every transition from said first mode to said second mode.

3. A microprocessor comprising:

a central processing unit;

an on-chip memory array for storing instructions executable on said central processing unit;

an external memory interface capable of reading from and writing to an off-chip memory instructions executable on said central processing unit; and

a configurable program memory controller in communication with said central processing unit, said on-chip memory array, and said external memory interface, said configurable program memory controller having a plurality of operating modes, including a first mode in which it uses said on-chip memory array as a memory-mapped on-chip memory, and a second mode in which it uses said on-chip memory array as a cache on-chip memory, said configurable program memory controller operable to always load said on-chip memory from predetermined locations of off-chip memory via said external memory interface upon each and every transition between said second mode to said first mode.

4. The microprocessor of claim 3, further comprising:

a cache tag memory having a plurality of validity bits, each validity bit indicating a valid state or an invalid state for a corresponding portion of said on-chip memory array; and

wherein said configurable program memory controller is further operable to always reset all validity bits to indicate said invalid state upon each and every transition from said first mode to said second mode.

5. A method of operating a microprocessor having a central processing unit, an on-chip memory operable in a first mode and a second mode and an external memory interface capable of reading from and writing to off-chip memory, the method comprising the steps of:

operating said on-chip memory as a memory-mapped memory having a predetermined range of addresses when in said first mode;

operating said on-chip memory as a cache memory when in said second mode; and

transiting from said second mode to said first mode only following a cache miss.

6. The method of operating a microprocessor of claim 5, further comprising the step of:

always indicating all data within said on-chip memory is invalid upon each and every transition from said first mode to said second mode.

8. The method of operating a microprocessor of claim 6, further comprising the step of:

always indicating all data within said on-chip memory is invalid upon each and every transition from said first mode to said second mode.

7. A method of operating a microprocessor having a central processing unit, an on-chip memory operable in a first mode and a second mode and an external memory interface capable of reading from and writing to off-chip memory, the method comprising the steps of:

operating said on-chip memory as a memory-mapped memory having a predetermined range of addresses when in said first mode;

operating said on-chip memory as a cache memory when in said second mode; and

always loading said on-chip memory from predetermined locations of said off-chip memory via said external memory interface upon transiting from said second mode to said first mode.