System and method for executing platform-independent code on a co-processor

• US 6,321,323 B1
• Filed: 06/27/1997
• Issued: 11/20/2001
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Valia, Rohit, Nugroho, Sofyan I., Srivastava, Anil K.
• Primary Examiner(s): COURTENAY III, ST JOHN
• Application Number:
  US08/884,186
• Time in Patent Office: 1,607 Days
• Field of Search: 709/1, 709/100-108, 709/400, 710/14, 710/22, 712/1, 712/28, 712/30, 712/31, 712/34, 712/25, 712/26, 712/27, 717/4, 717/5, 711/5, 711/103, 713/1, 713/2, 713/100
• US Class Current: 712/34
• CPC Class Codes: G06F 8/443 Optimisation
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A system and method for executing platform-independent code on a co-processor is described. The system includes a processor, a main memory and the co-processor, each interconnected with each other. The processor and the co-processor operate under control of an operating system. A memory manager operatively coupled to the operating system initializes a runtime environment including an address space in the main memory for the platform-independent code. A runtime shim operatively coupled to the operating system provides the initialized runtime environment to the co-processor through the operating system. The co-processor executes the platform-independent code responsive to the runtime shim with reference to the address space in the main memory.

Claims

1. A system for executing platform-independent code on a co-processor, the system comprising a processor, a main memory and the co-processor, each interconnected with each other, the processor and the co-processor operating under control of an operating system, the system comprising:

a memory manager operatively coupled to the operating system for initializing a runtime environment comprising an address space in the main memory for the platform-independent code;

a runtime shim operatively coupled to the operating system for providing the initialized runtime environment to the co-processor through the operating system;

the co-processor for executing the platform-independent code responsive to the runtime shim with reference to the address space in the main memory; and

a programmable read only memory operatively coupled to the co-processor for storing core classes of the platform-independent code.

2. A system according to claim 1, the memory manager further comprising:

an address space allocator for allocating the address space in the main memory for the platform-independent code; and

a code loader for loading, responsive to the memory manager, the platform-independent code into the allocated address space in the main memory using the operating system.

3. A system according to claim 2, wherein the platform-independent code comprises at least one reference to an object class external to the platform-independent code, the address space allocation unit allocating additional address space in the main memory for the object class for each such at least one reference, and the code loader loading the object class for each such at least one reference into the additional allocated address space in the main memory.

4. A system according to claim 2, wherein the platform-independent code is locked into the main memory by the memory manager.

5. A system according to claim 1, wherein an interrupt signal is sent to the co-processor from the runtime shim via the operating system and a location in the main memory for the address space is sent to the co-processor from the runtime shim.

6. A system according to claim 5, further comprising a device driver functionally interposed within the operating system between the runtime shim and the co-processor for interfacing between the runtime shim and the co-processor.

7. A system according to claim 1, wherein the system further comprises a buffer operatively interposed between the main memory and the co-processor, the main memory further comprising a plurality of memory pages, wherein the co-processor receives a pointer pointing to a starting location in the main memory for the address space for the platform-independent code, the starting location being associated with a first such memory page in the main memory, retrieves using the pointer the first such memory page from the main memory into the buffer, retrieves using the pointer another such memory page for each such instruction in the platform-independent code occurring on a different such memory page than retrieved into the buffer, and executes the retrieved instruction on the co-processor.

8. A system according to claim 7, wherein the co-processor operates directly responsive to the platform-independent code, the co-processor directly executing the retrieved instruction.

9. A system according to claim 7, wherein the co-processor operates responsive to a non-native instruction set different from the platform-independent code, the co-processor further comprising translation logic for translating the retrieved instruction into an equivalent instruction in the non-native instruction set using the translation logic, the co-processor executing the equivalent instruction.

10. A system according to claim 7, wherein the co-processor verifies the security integrity of the platform-independent code.

11. A system according to claim 7, wherein the platform-independent code comprises at least one reference to a core object class external to the platform-independent code, the co-processor further comprising a core object class library storing a plurality of core object classes, the co-processor retrieving the core object class for each such reference from the core object class library and dynamically linking the retrieved core object class to the platform-independent code.

12. A system according to claim 7, wherein the platform-independent code comprises at least one reference to a system service call external to the platform-independent code, the processor processing the system call by cooperatively interfacing to the runtime shim.

13. A method using a computer for executing platform-independent code on a co-processor, the computer comprising a processor, a main memory, a programmable read only memory, and the co-processor, each interconnected with each other, the processor and the co-processor operating under control of an operating system, the method comprising the steps of:

initializing a runtime environment comprising an address space in the main memory for the platform-independent code using a memory manager operatively coupled to the operating system;

providing the initialized runtime environment to the co-processor through the operating system using a runtime shim operatively coupled to the operating system; and

executing the platform-independent code on the co-processor responsive to the runtime shim with reference to the address space in the main memory;

wherein the co-processor executes the core classes of the platform-independent code from the programmable read only memory.

14. A method according to claim 13, the step of initializing the runtime environment further comprising the steps of:

allocating the address space in the main memory for the platform-independent code using the runtime shim; and

loading, responsive to the runtime shim, the platform-independent code into the allocated address space in the main memory using the operating system.

15. A method according to claim 14, wherein the platform-independent code comprises at least one reference to an object class external to the platform-independent code, the step of allocating the address space further comprising allocating additional address space in the main memory of the object class for each such at least one reference, the step of loading further comprising loading the object class for each such at least one reference into the additional allocated address space in the main memory.

16. A method according to claim 14, further comprising the step of locking the platform-independent code into the main memory.

17. A method according to claim 13, the step of providing initialized runtime environment further comprising the steps of:

sending an interrupt signal to the co-processor from the runtime shim via the operating system; and

sending a location in the main memory for the address space to the co-procssor from the runtime shim.

18. A method according to claim 17, further comprising the step of interfacing between the runtime shim and the co-processor via a device driver functionally interposed within the operating system between the runtime shim and the co-processor.

19. A method according to claim 13, wherein the system further comprises a buffer operatively interposed between the main memory and the co-processor, the main memory further comprising a plurality of memory pages, the step of executing the platform-independent code further comprising the steps of:

receiving a pointer into the co-processor pointing to a starting location in the main memory for the address space for the platform-independent code, the starting location being associated with a first such memory page in the main memory;

retrieving using the pointer the first such memory page from the main memory into the buffer;

retrieving using the pointer another such memory page for each such instruction in the platform-independent code occurring on a different such memory page than retrieved into the buffer; and

executing the retrieved instruction on the co-processor.

20. A method according to claim 19, wherein the co processor operates directly responsive to the platform-independent code, the step of executing the retrieved instruction further comprising the step of directly executing the retrieved instruction on the co-processor.

21. A method according to claim 19, wherein the co-processor operates responsive to a non-native instruction set different from the platform-independent code, the co-processor further comprising translation logic, the step of executing the retrieved instruction further comprising the steps of:

translating the retrieved instruction into an equivalent instruction in the non-native instruction set using the translation logic; and

executing the equivalent instruction on the co-processor.

22. A method according to claim 19, further comprising the step of verifying the security integrity of the platform-independent code using the co-processor.

23. A method according to claim 19, wherein the platform-independent code comprises at least one reference to a core object class external to the platform-independent code and the co-processor further comprises a core object class library storing a plurality of core object classes, the step of retrieving further comprising the steps of:

retrieving the core object class for each such reference from the core object class library; and

dynamically linking the retrieved core object class to the platform-independent code.

24. A method according to claim 19, wherein the platform-independent code comprises at least one reference to a system service call external to the platform-independent code, the step of retrieving further comprising the step of processing the system service call on the processor cooperatively interfacing to the runtime shim.

25. A method according to claim 24, the step of processing the system service call further comprising the steps of:

sending a system service call interrupt from the co-processor to the runtime shim;

receiving the system service call interrupt in the runtime shim and, in response, sending a system service call to the operating system;

performing the system service on the processor;

notifying the runtime shim upon completion of the system service using the processor; and

notifying the co-processor upon completion of the system service call using the runtime shim.

26. An apparatus for efficiently executing platform-independent code in a computer system, the computer system including a processor and a main memory, each interconnected with each other, the apparatus comprising:

interfacing logic interconnecting the apparatus with the processor and the main memory and comprising channels for exchanging control, data and address signals with the processor and the main memory;

a co-processor executing the platform-independent code in coordination with but independently from the processor;

a buffer interconnected with the co-processor and comprising a plurality of storage locations in which are staged segments of the platform-independent code prior to execution by the co-processor;

a programmable read only memory for storing core classes of the platform-independent code;

a direct memory access (DMA) controller interconnected with the buffer and interfacing directly to the main memory through the interfacing logic, the DMA controller staging the segments of the platform-independent code into the buffer from the main memory; and

a bus internal to the apparatus interconnecting the interfacing logic, the co-processor, the direct memory access controller, and the programmable read only memory, the interfacing logic providing the control, data and address signals over the internal bus.

27. An apparatus according to claim 26, further comprising a programmable read only memory (PROM) comprising a plurality of storage locations in which are stored executable core program segments, the co-processor retrieving the executable core program segments in response to a core program call in the platform-independent code, the internal bus interconnecting the co-processor with the PROM.

28. An apparatus according to claim 26, further comprising a read only memory (ROM) comprising a plurality of storage locations in which are stored microcode instructions, the co-processor executing the platform-independent code in accordance with the microcode instructions, the internal bus interconnecting the co-processor with the ROM.

29. An apparatus according to claim 26, wherein the co-processor further comprises a processor configured to operate under control of an instruction set for the platform-independent code.

30. An apparatus according to claim 26, wherein the co-processor further comprises:

a processor configured to operate under control of an instruction set for the platform-specific code; and

translation logic converting the instruction set for the platform-specific code to an instruction set for the platform-independent code.

31. A method using a computer for facilitating execution of platform-independent program code on a co-processor, the computer including a processor, a main memory, a programmable read only memory, and the co-processor, each interconnected with each other, the method comprising the steps of:

initializing a runtime environment comprising an address space in the main memory in which is stored the platform-independent program code;

notifying the co-processor to begin execution of the platform-independent program code including providing the address space in the runtime environment to the co-processor; and

coordinating execution of the platform-independent program code by the co-processor with independent execution of other program code by the processor and managing the main memory between the address space in the runtime environment and the main memory used by the processor;

wherein the co-processor executes the core classes of the platform-independent code from the programmable read only memory.

32. A method according to claim 31, further comprising the step of processing system service call interrupts received from the co-processor.