Interface for compiling project variations in electronic design environments

• US 6,321,369 B1
• Filed: 10/27/1997
• Issued: 11/20/2001
• Est. Priority Date: 10/28/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rawls, Tamlyn V., Heile, Francis B.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/958,626
• Time in Patent Office: 1,485 Days
• Field of Search: 395/500.12, 395/500.19, 395/500.02, 395/500.04, 395/500.05, 716/1, 716/3, 716/4, 716/11, 716/18
• US Class Current: 716/102
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 8/60 Software deployment
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06Q 10/06 Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
• CPC Class Codes: G06Q 10/10 Office automation; Time management
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99954 Version management

Abstract

A method is provided in which a base design is generated in the form of one or more data files including assignment data. A variation design is created by adding at least one additional assignment associated with the variation design to the assignment data. The assignment data has an identifier that is associated with an entity defined within the base design, a first data field that can be used in making an assignment to the entity within the base design and a second data field for use in making the additional assignment to the entity within the variation design. The data files are compiled to generate a base output file and one or more variation output design files that can include one or more common result values. Comparison data is generated by comparing the common result values associated with the base design file and the variation design file. A design tool is provided for use with a computer system having a processor. The design tool includes a selector and a variation mechanism. Both the selector and variation mechanism are configured to run on the processor and are capable of accepting inputs from a user. The selector generates a base design in the form of one or more data files including assignment data. The variation mechanism generates a variation design by adding at least one additional assignment associated with the variation design.

Claims

1. A method for compiling a base design and a variation of an electronic design, the method comprising:

providing a graphical user interface;

providing a base design, said base design including one or more data files including assignment data;

creating a variation design by applying at least one variation assignment to a group of logic functions not provided in the assignment data of said base design, wherein the variation assignment to the group of logic functions specifies at least one of a style, logic option, clique assignment, position requirement, timing requirement, family, device, speed grade and global default parameter;

using said graphical user interface to display, for compilation, a list of designs including the base design and the variation design;

with the aid of said graphical user interface, selecting for compilation the base design and the variation design;

compiling both said base design and said variation design; and

outputting the compiled base design to a first file designated for said compiled base design and outputting the compiled variation design to a second file designated for said compiled variation design.

2. The method of claim 1, wherein the electronic design is a programmable logic device.

3. The method as recited in claim 1 further comprising comparing the compiled variation design to the compiled base design with the aid of said graphical user interface.

4. The method as recited in claim 1 wherein said variation design includes a representation of an entity within said variation design, which representation includes a first identifier specifying the entity defined within said base design, a second identifier specifying the variation assignment, and a tag identifying the variation assignment as a variation assignment.

5. The method as recited in claim 1 further comprising creating a new plurality of variation designs by further adding at least one additional variation assignment to each of said plurality of variation designs.

6. The method as recited in claim 5 wherein each of said variation designs includes a representation of an entity within said variation design, which representation includes a first identifier specifying the entity defined within said base design, a second identifier specifying the variation assignment, and a tag identifying the variation assignment as a variation assignment.

7. An apparatus for use in designing electronic designs, said apparatus comprising:

a selector configured to provide a base design in the form of one or more data files including assignment data; and

a variation mechanism configured to create a variation design by applying at least one variation assignment to a group of logic functions not provided in the assignment data of said base design, wherein the variation assignment to the group of logic functions specifies at least one of a style, logic option, clique assignment, position requirement, timing requirement, family, device, speed grade and global default parameter;

a compiler configured to compile the base design and the variation design; and

a graphical user interface for displaying a list of designs for compilation including the base design and the variation design, selecting said base design and said variation design and initiating compilation of said base design and said variation design.

8. The apparatus as recited in claim 7 wherein said graphical user interface provides a tool coupled to said variation mechanism for creating said variation design.

9. The apparatus as recited in claim 7 wherein said variation mechanism is further configured to generate output data comparing compiled versions of said base design circuit and said variation design circuit.

10. The apparatus as recited in claim 7 wherein said assignment data and said variation assignment include at least one attribute that is selected from a group consisting of a logic option, a timing requirement, a position requirement, and a clique assignment.

11. The apparatus as recited in claim 7 wherein said variation design includes a representation of an entity within said variation design, which representation includes a first identifier specifying the entity defined within said base design, a second identifier specifying the variation assignment, and a tag identifying the variation assignment as a variation assignment.

12. The apparatus as recited in claim 7 wherein said variation mechanism is further configured to create a new plurality of variation designs by further adding at least one of a plurality of variation assignments associated with each of said plurality of variation designs to said assignment data.

13. The apparatus as recited in claim 12 wherein each of said variation designs includes a representation of an entity within said variation design, which representation includes a first identifier specifying the entity defined within said base design, a second identifier specifying the variation assignment, and a tag identifying the variation assignment as a variation.

14. A design tool for use with a computer system having a processor, said design tool comprising:

a selector configured to run on said processor and capable of accepting selection inputs from a user via said computer system and providing a base design in the form of one or more data files including assignment data;

a variation mechanism configured to run on said processor and responsive to variation inputs from said user via said computer system and said selector, said variation mechanism being capable of generating a variation design by adding at least one variation assignment to a group of logic functions to said assignment data wherein the variation assignment to the group of logic functions specifies at least one of a style, logic option, clique assignment, position requirement, timing requirement, family, device, speed grade and global default parameter; and

a compiler configured to compile the base design and the variation design; and

a graphical user interface for displaying a list of designs for compilation including the base design and the variation design, selecting said base design and said variation design and initiating compilation of said base design and said variation design.

15. The design tool as recited in claim 14 wherein said graphical user interface provides a tool coupled to said variation mechanism for creating said variation design.

16. The design tool as recited in claim 15 wherein said variation mechanism is further configured to generate output data comparing compiled versions of said base design and said variation design.

17. The design tool as recited in claim 15 wherein said compiled base design is in a format suitable for use with a programming device configured to produce an integrated circuit according to instructions in said base design.

18. The design tool as recited in claim 14 wherein said variation assignment includes at least one attribute that is selected from a group consisting of a logic option, a timing requirement, a position requirement, and a clique assignment.

19. The design tool as recited in claim 14 wherein said variation design includes a representation of an entity within said variation design, which representation includes a first identifier specifying the entity defined within said base design, a second identifier specifying the variation assignment, and a tag identifying the variation assignment as a variation assignment.

20. A computer-readable media having a design tool as recited in claim 14 embodied thereon.

21. A computer-readable media having a stored data structure suitable for use in a computer system having circuit design tool abilities capable of supporting multiple variations of a circuit design, the stored data structure comprising:

an identifier associated with an entity defined within a base design;

first data associated with an assignment to said entity within said base design; and

second data associated with a variation assignment to a group of logic functions of said entity within a variation design, wherein the variation assignment to the group of logic functions specifies at least one of a style, logic option, clique assignment, position requirement, timing requirement, family, device, speed grade and global default parameter.