Package of integrated circuits and vertical integration

• US 6,322,903 B1
• Filed: 12/06/1999
• Issued: 11/27/2001
• Est. Priority Date: 12/06/1999
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Savastiouk, Sergey, Siniaguine, Oleg
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Huynh, Yennhu B.
• Application Number:
  US09/456,225
• Time in Patent Office: 722 Days
• Field of Search: 438/616, 438/617, 438/118, 438/107, 438/112, 438/108, 438/113, 438/615, 438/119, 438/618, 438/315, 438/455-459, 438/598, 438/599
• US Class Current: 428/617
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/1357 Single coating layer
• CPC Class Codes: H01L 2224/136 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 428/12507 : More than two components

Abstract

A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.

Claims

1. A fabrication method comprising:

forming one or more vias in a first side of a first substrate;

forming a conductive contact in each of the vias so that each contact is not exposed on a second side of the first substrate;

exposing each contact on the second side of the first substrate with a blanket process which includes removing material from the second side of the first substrate, wherein the blanket process causes each contact to protrude from the second side of the first substrate; and

bonding at least one contact on the second side of the first substrate to a wiring substrate so that the first substrate or a portion thereof becomes directly attached to the wiring substrate, wherein the wiring substrate is a non-semiconductor substrate.

2. The method of claim 1 wherein the first substrate is a semiconductor wafer, the bonding is preceded by dicing the wafer into one or more dice, and the bonding results in at least one die being directly attached to the wiring substrate.

3. The method of claim 1 wherein the first substrate is a wafer, and the method further comprises, before said bonding, bonding the first side of the first substrate to a second substrate to manufacture a vertical integrated circuit.

4. A method for fabricating a vertical integrated circuit, the method comprising:

providing a vertically integrated stack of two or more structures M(1), . . . M(N), wherein each structure comprises one or more contacts directly attached to one or more contacts of another one of said structures, wherein the structure M(N) is an end structure in the stack, and the structure M(N) comprises a first side and a second side, the second side not being attached to any other one of said structures;

processing the first side of the end structure M(N) of the stack with a blanket process comprising blanket removal of material from the second side, wherein the blanket process exposes one or more first contacts protruding from the second side by at least a predetermined amount.

5. The method of claim 4 further comprising bonding each first contact to a structure M(N+1), wherein the blanket process exposes one or more features which are used as alignment marks during the bonding to the structure M(N+1).

6. The method of claim 4 wherein:

the structure M(N) comprises a wafer which comprises one or more dice;

the method comprises separating the stack into separate parts, at least one of the parts including a die from the structure M(N);

the structure M(N) has a first side attached to the structure M(N−

1), and before the blanket process the structure M(N) has one or more vias made in the first side at the boundary of at least one of the dice, wherein each via is made part way through the structure M(N); and

the blanket process results in the one or more vias becoming exposed on the second side of the structure M(N).

12. The method of claim 4 wherein each of the structures M(1), . . . M(N) comprises a semiconductor integrated circuit.

13. The method of claim 6 wherein each of the structures M(1), . . . M(N) comprises a semiconductor wafer.

14. The method of claim 12 wherein providing the stack of structures comprises manufacturing each of the structures M(1), . . . M(N) and attaching these structures together to form the stack of structures.

15. The method of claim 6 wherein separating the stack comprises dicing the stack.

7. A fabrication method comprising:

providing a structure S1 comprising a semiconductor substrate with circuitry adjacent to a first side of the structure;

removing material from a second side of the structure S1 to expose one or more first contact structures, wherein the material is removed at least until the one or more first contact structures protrude from the second side by at least a predetermined amount, and wherein the material removal is a blanket removal process;

depositing flowable material on the second side, wherein the flowable material is dielectric when hardened;

subjecting the flowable material to a blanket material-removal process at least until the one or more first contact structures protrude on the second side by at least a predetermined amount, so that after the removal the hardened flowable material covers the substrate on the second side.

8. The method of claim 7 wherein each first contact structure comprises:

a conductive contact; and

a dielectric covering the conductive contact on the second side; and

wherein the removal process is followed by removing the dielectric to expose the conductive contact in each first contact structure, wherein after the dielectric removal the hardened flowable material still covers the substrate on the second side.

9. A semiconductor fabrication method comprising:

making one or more vias in a first side of a first semiconductor wafer along one or more scribe lines;

bonding the first side of the first wafer to a second semiconductor wafer; and

removing material from a second side of the first wafer until the vias become through holes.

10. The method of claim 9 wherein the vias become through holes during a blanket dry etch of the first wafer.

11. The method of claim 9 wherein the one or more vias form a groove completely surrounding at least one die in the first wafer.

16. A fabrication method comprising:

forming one or more vias in a first side of a first substrate;

forming a conductive contact in each of the vias so that each contact is not exposed on a second side of the first substrate;

exposing each contact on the second side of the first substrate with a blanket process which includes removing material from the second side of the first substrate, wherein the blanket process causes each contact to protrude from the second side of the first substrate; and

bonding at least one contact on the second side of the first substrate to a printed circuit board (PCB) so that the first substrate or a portion thereof becomes directly attached to the PCB.

17. The method of claim 16 wherein the first substrate is a semiconductor wafer, the bonding is preceded by dicing the wafer into one or more dice, and the bonding results in at least one die being directly attached to the PCB.

18. The method of claim 16 wherein the first substrate is a wafer, and the method further comprises, before said bonding, bonding the first side of the first substrate to a second substrate to manufacture a vertical integrated circuit.

19. A fabrication method comprising:

forming one or more vias in a first side of a first substrate;

forming a conductive contact in each of the vias so that each contact is not exposed on a second side of the first substrate;

exposing each contact on the second side of the first substrate with a blanket process which includes removing material from the second side of the first substrate, wherein the blanket process causes each contact to protrude from the second side of the first substrate; and

bonding at least one contact on the second side of the first substrate to a wiring substrate so that the first substrate or a portion thereof becomes directly attached to the wiring substrate, wherein the wiring substrate is a semiconductor substrate without any active devices.

20. The method of claim 19 wherein the first substrate is a semiconductor wafer, the bonding is preceded by dicing the wafer into one or more dice, and the bonding results in at least one die being directly attached to the wiring substrate.

21. The method of claim 19 wherein the first substrate is a wafer, and the method further comprises, before said bonding, bonding the first side of the first substrate to a second substrate to manufacture a vertical integrated circuit.

22. A fabrication method comprising:

forming one or more first vias in a first side of a first substrate;

forming a first conductive contact in each of the first vias so that each first contact is not exposed on a second side of the first substrate;

forming one or more second vias in a first side of a second substrate;

forming a second conductive contact in each of the second vias so that each second contact is not exposed on a second side of the second substrate;

attaching the first side of the first substrate to the first side of the second substrate;

after the attaching operation, removing material from the second side of the first substrate to expose the one or more first contacts, and bonding the one or more exposed first contacts to one or more conductive contacts on a third substrate; and

then

removing material from the second side of the second substrate to expose the one or more second contacts, and bonding the one or more exposed second contacts to one or more conductive contacts on a fourth substrate.

23. The method of claim 22 wherein each of the first and second substrates is a semiconductor substrate, and the method further comprises manufacturing a transistor region in at least one of the first and second substrates before the attaching operation.

24. The method of claim 22 wherein each of the first and second substrates is a semiconductor substrate, and the method further comprises manufacturing a transistor region in each of the first and second substrates before the attaching operation.

25. The method of claim 22 wherein the first, second and third substrates are semiconductor substrates, and the method further comprises manufacturing a transistor region in at least one of the first, second and third substrates before bonding a first contact to a contact on the third substrate.

26. The method of claim 22 wherein the first, second and third substrates are semiconductor substrates, and the method further comprises manufacturing a transistor region in each of the first, second and third substrates before bonding a first contact to a contact on the third substrate.

27. The method of claim 22 wherein the first, second, third and fourth substrates are semiconductor substrates, and the method further comprises manufacturing a transistor region in at least one of the first, second, third and fourth substrates before bonding of the first and second contacts.

28. The method of claim 22 wherein the first, second and third substrates are semiconductor substrates, and the method further comprises manufacturing a transistor region in each of the first, second, third and fourth substrates before bonding of the first and second contacts.

29. The method of claim 22 wherein attaching the first side of the first substrate to the first side of the second substrate comprises bonding one or more contacts on the first side of the first substrate to one or more contacts on the first side of the second substrate.