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Dual floating gate programmable read only memory cell structure and method for its fabrication an operation

  • US 6,323,088 B1
  • Filed: 08/29/2000
  • Issued: 11/27/2001
  • Est. Priority Date: 04/08/1998
  • Status: Expired due to Term
First Claim
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1. A method of forming a memory cell comprising the steps of:

  • forming a first floating gate region on a silicon substrate;

    forming a second floating gate region on said silicon substrate;

    said second floating gate region being adjacent to and electrically isolated from said first floating gate region;

    forming a sidewall insulator on at least one of said first and second floating gate regions;

    forming an insulating layer over said first and second floating gate regions;

    forming a control gate region over said insulating layer and over said first and second floating gate regions;

    forming active doped regions in said substrate such that said first and second floating gate regions are located at least in part between said active doped regions; and

    forming electrical interconnects with said active doped and control gate regions, at least one of the electrical interconnects to an active doped region also connecting with said sidewall insulator.

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