Semiconductor device with trenched substrate and method

• US 6,323,090 B1
• Filed: 06/09/1999
• Issued: 11/27/2001
• Est. Priority Date: 06/09/1999
• Status: Expired due to Term

• Current Assignee: Littelfuse Incorporated
• Original Assignee: IXYS Corporation (Littelfuse Incorporated)
• Inventors: Zommer, Nathan
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Smith, Bradley
• Application Number:
  US09/332,638
• Time in Patent Office: 902 Days
• Field of Search: 438/271, 438/270, 438/268, 438/156, 438/416, 438/429, 438/276
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A transistor structure has a recess formed in the upper surface of its base layer, an epitaxial (epi) layer grown on the upper surface in a manner to create a surface depression in the outer surface of the epi layer, the surface depression being generally aligned with the recess. A semiconductor element, such as a well or a gate, is formed on the epi layer aligned with the recess.

Claims

1. A method for modifying a performance characteristic of a semiconductor device while producing the semiconductor device comprising:

creating a recess in an upper surface of a base layer, the base layer comprising a chosen one of a p+ or n+ substrate;

growing an epitaxial (epi) layer on the upper surface, the epi layer having an outer surface; and

forming, on the epi layer, a semiconductor device element associated with the recess.

2. The method according to claim 1 wherein the growing step is carried out to create a surface depression in the outer surface of the epi layer generally aligned with the recess.

3. The method according to claim 2 further comprising processing the outer surface of the epi layer to at least partially remove said surface depression from said outer surface prior to the forming step.

4. The method according to claim 1 wherein the creating step is carried out with the substrate comprising an n+ substrate and the growing step is carried out with the epi layer comprising an n−

epi layer.

5. The method according to claim 1 wherein the forming step is carried out so the semiconductor device element is generally aligned with the recess.

6. The method according to claim 1 wherein the forming step comprises the step of forming a gate oxide region.

7. The method according to claim 1 wherein the forming step comprises the step of forming a doped well.

8. The method according to claim 1 further comprising growing a buffer layer on the upper surface prior to the epi layer growing step.

9. A method for modifying a performance characteristic of a semiconductor device while producing the semiconductor device comprising:

creating a recess in an upper surface of a base layer;

growing an epitaxial (epi) layer on the upper surface, the epi layer having an outer surface;

the growing step being carried out to create a surface depression in the outer surface of the epi layer generally aligned with the recess;

processing the outer surface of the epi layer to at least partially remove said surface depression from said outer surface, and then forming, on the epi layer, a semiconductor device element associated with the recess.