Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices

• US 6,323,106 B1
• Filed: 12/29/1999
• Issued: 11/27/2001
• Est. Priority Date: 09/02/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Puchner, Helmut, Huang, Shih-Fen
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/474,666
• Time in Patent Office: 699 Days
• Field of Search: 438/296, 438/424, 438/438, 438/435, 438/275, 438/981
• US Class Current: 438/433
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

Provided is a technique for fabrication of a nitrided gate oxide and shallow trench isolation (STI) oxide liner in a semiconductor depletion into STI oxide and the RNCE in CMOS devices by introducing nitrogen to the STI edges of the p-well. This technique improves isolation performance and is also effective to harden the oxide to reduce boron penetration. Nitridization of the STI liner may be conducted on its own or in combination with gate oxide nitridization, both with beneficial effect with regard to the RNCE. The nitridization may also be focussed on the channel region of the gate oxide in particular in order to mitigate RSCE.

Claims

1. A process for forming a shallow trench isolation in a semiconductor device, comprising:

depositing a pad oxide layer on the surface of a silicon substrate;

forming a shallow trench in the substrate;

forming an oxide liner in the shallow trench;

implanting nitrogen into the oxide trench liner and underlying substrate silicon at the oxide/silicon interface; and

filling the trench with oxide.

2. The process of claim 1, further comprising forming and patterning a nitride mask layer on the pad oxide layer prior to forming the shallow trench.

3. The process of claim 1, further comprising removing the mask and planarizing the semiconductor device down to the substrate.

4. The process of claim 3, further comprising forming a gate oxide on the substrate and shallow trench isolation.

5. The process of claim 4, further comprising:

masking the gate oxide in a region where a thicker gate oxide is desired;

implanting nitrogen into an unmasked portion of said gate oxide to form an oxynitride layer overlying a silicon nitride layer;

removing the mask; and

further oxidizing the oxide and oxynitide portions of the original oxide layer on the substrate.

6. The process of claim 5, wherein the gate oxide is grown by thermal oxidation.

7. The process of claim 5, wherein said masking is conducted over an n-well region in said substrate.

8. The process of claim 7, wherein an unmasked p-well region of said substrate is nitridized such that nitrogen is implanted into the gate oxide and underlying substrate silicon at the oxide/silicon interface in that region.

9. The process of claim 1, wherein said trench is formed about 0.05 to 0.5 μ

m micron deep by etching.

10. The process of claim 1, wherein the nitrogen implant is conducted using a series of tilted nitrogen implants.

11. The process of claim 10, wherein the series of tilted nitrogen implants is conducted at about a 22°

tilt angle and rotating twist angle.

12. The process of claim 10, wherein the series of tilted nitrogen implants is conducted at about a 90°

angle to the substrate.

13. The process of claim 10, wherein the series of tilted nitrogen implants is conducted such that about 1 to 10% of nitrogen is implanted in said oxide trench liner.

14. The process of claim 1, wherein the trench is filled by a chemical vapor deposition technique selected from HDP-CVD and APCVD.

15. The process of claim 1 wherein said nitrogen implant is conducted with N⁺ or N² species using 10-100 keV energy and 1e14 cm-2 to 5e15 cm-2 implantation dose.

16. A method of reducing reverse narrow channel effect in a semiconductor device having a shallow trench isolation separating n-well and p-well regions in a silicon substrate, comprising:

implanting nitrogen into a oxide trench liner of the shallow trench isolation and underlying substrate silicon at the oxide/silicon interface;

filling the trench with oxide to form a shallow trench isolation;

forming a gate oxide on the substrate and shallow trench isolation;

masking the gate oxide over the n-well region in said substrate;

implanting nitrogen into an unmasked portion of said gate oxide to form an oxynitride layer overlying a silicon nitride layer;

removing the mask; and

further oxidizing the oxide and oxynitide portions of the original oxide layer on the substrate.

17. The method of claim 16, wherein said semiconductor device comprises a narrow channel.

18. The method of claim 17, wherein said narrow channel is less than about 0.5 micron wide.