Self-aligned silicon carbide LMOSFET

• US 6,323,506 B1
• Filed: 12/21/1999
• Issued: 11/27/2001
• Est. Priority Date: 12/21/1999
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Alok, Dev
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nhu, David
• Application Number:
  US09/469,454
• Time in Patent Office: 707 Days
• Field of Search: 257/77, 257/288, 257/330, 257/332, 257/333, 257/336, 257/339, 257/343, 257/344, 257/461
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) having a self-aligned gate, includes a first layer of SiC semiconductor material having a p-type conductivity, and a second layer of SiC semiconductor material having an n-type conductivity formed on the first layer. Source and drain regions having n-type conductivities are formed in the second SiC semiconductor layer. The n-type conductivities of the source and drain regions are greater than the n-type conductivity of the second SiC layer. A trench extends through the second SiC semiconductor layer and partially into the first SiC semiconductor layer. The trench is coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material. The layers of oxide and metallic material form a gate structure. A channel region is defined in the first layer beneath the gate structure, and electrical contacts associated with the source and drain regions, and the gate structure, establish source, drain, and gate electrodes of the LMOSFET.

Claims

1. A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) having a self-aligned gate, the LMOSFET comprising:

a first layer of silicon carbide semiconductor material having a p-type conductivity;

a second layer of silicon carbide semiconductor material having an n-type conductivity formed on the first layer;

source and drain regions having n-type conductivities formed in the second silicon carbide semiconductor layer, the n-type conductivities of the source and drain regions being greater than the n-type conductivity of the second silicon carbide layer;

a trench extending through the second silicon carbide semiconductor layer and partially into the first silicon carbide semiconductor layer so that the source and drain regions are substantially lateral thereto, the trench coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material, the layers of oxide and metallic material forming a gate structure;

a channel region defined in the first layer beneath the gate structure; and

electrical contacts associated with the source and drain regions, and the gate structure thereby establishing source, drain, and gate electrodes of the LMOSFET.

2. The LMOSFET according to claim 1, further comprising a substrate which supports the first and second silicon carbide semiconductor layers.

3. The LMOSFET according to claim 1, wherein the first layer of silicon carbide semiconductor material is an epitaxial layer.

4. The LMOSFET according to claim 1, wherein the second layer of silicon carbide semiconductor material is an epitaxial layer.

5. The LMOSFET according to claim 4, wherein the epitaxial second layer of silicon carbide semiconductor material defines a drift region that extends laterally from the drain region to the gate structure, the gate structure being substantially aligned with the source and drift regions.

6. The LMOSFET according to claim 1, wherein the source and drain regions each have a depth which is at least equal to the thickness of the second layer of silicon carbide material.

7. The LMOSFET according to claim 6, wherein the source and drain regions extend partially into the first layer of silicon carbide semiconductor material and each have a depth which is slightly less than the depth of the trench.

8. The LMOSFET according to claim 1, wherein the source and drain regions are implanted regions.