Insulated gate semiconductor device and manufacturing method thereof
First Claim
1. An insulated gate type semiconductor device, comprising:
- a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body having, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, and a second main electrode electrically connected to said lower main surface, said first main electrode being electrically connected to said upper main surface in a first region defined substantially in a zonal form along said trenches in said upper main surface interposed between adjacent said trenches, said third semiconductor layer being exposed in a second region and third regions defined in said upper main surface interposed between adjacent said trenches, said third regions being defined substantially in zonal forms without discontinuance adjacently to an inside of adjacent said trenches and along the same, and said second region being selectively defined in a part of a region interposed between adjacent said third regions, and said insulated gate type semiconductor device further comprising, overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer.
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Abstract
An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N+ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N+ emitter layer (206). Furthermore, the ladder-like N+ emitter layer (206) is formed adjacent to the trench (7), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.
38 Citations
15 Claims
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1. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body having, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, and a second main electrode electrically connected to said lower main surface, said first main electrode being electrically connected to said upper main surface in a first region defined substantially in a zonal form along said trenches in said upper main surface interposed between adjacent said trenches, said third semiconductor layer being exposed in a second region and third regions defined in said upper main surface interposed between adjacent said trenches, said third regions being defined substantially in zonal forms without discontinuance adjacently to an inside of adjacent said trenches and along the same, and said second region being selectively defined in a part of a region interposed between adjacent said third regions, and said insulated gate type semiconductor device further comprising, overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer.- View Dependent Claims (2)
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3. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, and a conductive layer having platinum silicide and interposed between said first main electrode and said upper main surface, and said first main electrode and said second and third semiconductor layers being electrically connected through the conductive layer, and said insulated gate type semiconductor device further comprising, overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer.- View Dependent Claims (4)
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5. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface entered between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, and overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
Jpr×
ρ
pn×
Lmax and Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of said insulated gate type semiconductor device is caused to flow between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer.
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6. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, and overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
n×
Jpr×
ρ
pn×
Lmax and Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is caused to flow between said first main electrode and said second main electrode, a ratio n of a magnitude of the main current when a short-circuit load is connected between said first main electrode and said second main electrode and said rated current, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer.
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7. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, and overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer.
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8. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, said semiconductor base body being single crystal and said upper main surface of said semiconductor base body is along a <
100>
crystal plane, anda thickness of said second semiconductor layer and a shape of said plurality of trenches are set so that a boundary of said first semiconductor layer and said second semiconductor layer is located below an intersection of a plane including an opening end of said trench in said upper main surface and inclined by an inclination angle of 45°
with respect to said upper main surface and a wall surface of said trench adjacent to that trench.
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9. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, and overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer, andsaid insulated gate type semiconductor device having a plurality of insulated gate type semiconductor elements each having one of said trenches which are arranged substantially in said stripe form in said semiconductor base body and having sensing means for detecting the magnitude of the main current or a temperature of said semiconductor base body, wherein said sensing means includes plural number of said insulated gate type semiconductor elements.
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10. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, and overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
m Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer, whereina plurality of insulated gate type semiconductor elements having one of said trenches for each and having a same structure are arranged substantially in a stripe form at equal intervals in said semiconductor base body along said upper and lower main surfaces, said first main electrode is connected to said plurality of insulated gate semiconductor elements at said upper main surface of said semiconductor base body, and said insulated gate type semiconductor device further comprises, an external electrode provided outside said semiconductor base body for making an electric connection between said insulated gate type semiconductor device and an external device, a plurality of interconnections each having one end connected to said first main electrode and another end connected to said external electrode to electrically connect said first main electrode and said external electrode, and each of said plurality of interconnections being connected to each of a plurality of unit regions imaginarily defined by nearly equally dividing a region occupied by said plurality of insulated gate type semiconductor elements in said upper main surface. - View Dependent Claims (11, 12)
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13. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, and overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer, andsaid semiconductor base body having a plurality of insulated gate type semiconductor elements, said plurality of insulated gate type semiconductor elements having one of said trenches for each and being arranged in a substantially linear stripe form along said upper and lower main surfaces, and said insulated gate type semiconductor device further comprising, an external electrode provided outside said semiconductor base body to make an electric connection between said insulated gate type semiconductor device and an external device, and an interconnection having its one end connected to said first main electrode and the other end connected to said external electrode to electrically connect said first main electrode and said external electrode, wherein said interconnection is connected to said first main electrode so that a direction of said interconnection and a direction of said insulated gate type semiconductor element intersect at an angle in the range of 20°
to 160°
.- View Dependent Claims (14)
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15. An insulated gate type semiconductor device, comprising:
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a semiconductor base body having an upper main surface and a lower main surface, the semiconductor base body comprising, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer, said semiconductor base body having a plurality of trenches arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween, said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, said insulated gate type semiconductor device further comprising, a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, a second main electrode electrically connected to said lower main surface, and overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and a shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>
m×
Jpr×
ρ
pn×
Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value of and said rated current, and ratio resistance ρ
pn of said second semiconductor layer right under said third semiconductor layer, whereina plurality of insulated gate type semiconductor elements having one of said trenches for each are arranged in said semiconductor base body, and each of said plurality of insulated gate type semiconductor elements is formed in a linear form or in a smooth curve form, and accordingly the respective trench which belongs to each element is formed in a linear form or in a smooth curve form along the respective element, and no trench of any element intersects a trench which belongs to another insulated gate type semiconductor element so that none of the trenches of the insulated gate semiconductor elements cross each other.
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Specification