Insulated gate type semiconductor device and method of manufacturing thereof

• US 6,323,518 B1
• Filed: 09/13/1999
• Issued: 11/27/2001
• Est. Priority Date: 09/16/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakazawa, Yoshito, Sakamoto, Kozo, Yanokura, Eiji
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/394,047
• Time in Patent Office: 806 Days
• Field of Search: 257/355, 257/330
• US Class Current: 257/330
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Plural grooves are formed in a main surface of semiconductor layers on semiconductor substrate, and gate layers connected to a gate electrode are formed in the plural grooves through a gate insulating film, and then a body diffusion layer is formed between the gate layers, and afterwards, a source diffusion layer connected to a source electrode and a source diffusion layer connected to a source electrode are formed in an identical process.

Claims

1. An insulated gate type semiconductor device comprising:

a trench type insulated gate semiconductor element;

a lateral type insulated gate semiconductor element concerning an operation of said trench type insulated gate semiconductor element,

said trench type insulated gate semiconductor element including plural grooves provided in a main surface of a semiconductor layer in a semiconductor substrate, a gate layer connected to a first electrode, said gate layer being provided inside of said grooves through a gate insulating film, a second electrode provided on a surface of said semiconductor layer opposite to said main surface, and a diffusion layer connected to a third electrode, said diffusion layer being provided between each said gate layer,

said lateral type insulated gate semiconductor element including a main gate layer connected to a gate electrode, said main gate layer being provided on said semiconductor layer in said semiconductor substrate through another gate insulating film, and a drain diffusion layer connected to a drain electrode and a source diffusion layer connected to a source electrode which are provided in regions of said semiconductor layer between which a region facing said main gate layer is put,

wherein depth of said diffusion layer connected to said third electrode is not greater than depth of said source diffusion layer of said lateral type insulated gate semiconductor element.

2. An insulated gate type semiconductor device as in claim 1, wherein said gate insulating film of said trench type insulated gate semiconductor element is thicker than said another gate insulating film of said lateral type insulated gate semiconductor element.

3. An insulated gate type semiconductor device as in claim 2, further comprising an insulating film provided on said main surface of said semiconductor layer in said semiconductor substrate, and plural silicon layers of a diode which are provided on said insulating film, said plural silicon layers having film thickness smaller than that of said gate layer of said lateral type insulated gate semiconductor element and different conductivity type.

4. An insulating gate type semiconductor device as in claim 2, further comprising an insulating film provided on said main surface of said semiconductor layer in said semiconductor substrate, wherein a silicon layer of a resistor is provided on said insulating film, said silicon layer having film thickness smaller than that of said gate layer of said lateral type insulated gate semiconductor element.

5. An insulating gate type semiconductor device as in claim 2, further comprising an insulating film provided on said main surface of said semiconductor layer in said semiconductor substrate, wherein a silicon layer of a capacitor is provided on said insulating film, said silicon layer having film thickness smaller than that of said gate layer of said lateral type insulated gate semiconductor element, said capacitor having an electrode connected to said gate layer of said lateral type insulated gate semiconductor element and an electrode connected to said silicon layer.

6. An insulated gate type semiconductor device as in claim 1, further comprising an insulating film provided on said main surface of said semiconductor layer in said semiconductor substrate, and plural silicon layers of a diode which are provided on said insulating film, said plural silicon layers having film thickness smaller than that of said gate layer of said lateral type insulated gate semiconductor element and different conductivity type.

7. A method of manufacturing an insulated gate type semiconductor device as in claim 6 comprising:

forming plural grooves in a main surface of a semiconductor layer in said semiconductor substrate;

forming a gate layer for connection of said first electrode inside of said grooves through a gate insulating film;

forming a body diffusion layer between each said gate layer; and

then forming a diffusion layer for connection of said third electrode and a cathode or anode layer for said diode in an identical process.

8. An insulating gate type semiconductor device as in claim 1, further comprising an insulating film provided on said main surface of said semiconductor layer in said semiconductor substrate, wherein a silicon layer of a resistor is provided on said insulating film, said silicon layer having film thickness smaller than that of said gate layer of said lateral type insulated gate semiconductor element.

9. An insulating gate type semiconductor device as in claim 1, further comprising an insulating film provided on said main surface of said semiconductor layer in said semiconductor substrate, wherein a silicon layer of a capacitor is provided on said insulating film, said silicon layer having film thickness smaller than that of said gate layer of said lateral type insulated gate semiconductor element, said capacitor having an electrode connected to said gate layer of said lateral type insulated gate semiconductor element and an electrode connected to said silicon layer.

10. An insulating gate type semiconductor device as in claim 1, further comprising an overcurrent detection control circuit suppressing output current of said trench type insulated gate semiconductor element when value of said output current is excessive, wherein said overcurrent detection control circuit including said lateral type insulated gate semiconductor element as a main element is provided in said semiconductor substrate.

11. A power switch system comprising:

a insulated gate type semiconductor device as in claim 10 as a driving force which drives a load;

said switch system suppressing output current of said trench type insulated gate semiconductor element, when said output current value of said trench type insulated gate semiconductor element becomes excessive with overload, or when temperature of said semiconductor layer increases over a pre-determined temperature.

12. An insulating gate type semiconductor device as in claim 1, further comprising a temperature detection control circuit suppressing output current of said trench type insulated gate semiconductor element when temperature of said semiconductor layer is larger than a predetermined temperature, wherein said temperature detection control circuit including said lateral type insulated gate semiconductor element as a main element is provided in said semiconductor substrate.

13. A power switch system comprising:

a insulated gate type semiconductor device as in claim 12 as a driving force which drives a load;

said switch system suppressing output current of said trench type insulated gate semiconductor element, when said output current value of said trench type insulated gate semiconductor element becomes excessive with overload, or when temperature of said semiconductor layer increases over a pre-determined temperature.

14. A method of manufacturing an insulated gate type semiconductor device as in claim 1, comprising:

forming plural grooves in a main surface of a semiconductor layer in said semiconductor substrate;

forming a gate layer for connection of said first electrode inside of said grooves through a gate insulating film;

forming a body diffusion layer between each said gate layer; and

then forming a diffusion layer for connection of said third electrode.

15. A method of manufacturing an insulated gate type semiconductor device as in claim 11, further comprising a step of forming said gate layer for said trench type insulated gate semiconductor element and a gate layer for said lateral type insulated gate semiconductor element in an identical process.

16. A method of manufacturing an insulated gate type semiconductor device as in claim 1 comprising:

forming plural grooves in a main surface of a semiconductor layer in said semiconductor substrate;

forming a gate layer for connection of said first electrode inside of said grooves through a gate insulating film;

forming a body diffusion layer between each said gate layer; and

then forming a diffusion layer for connection of said third electrode and a source diffusion layer for said lateral type insulated gate semiconductor element in an identical process.

17. A method of manufacturing an insulated gate type semiconductor device as in claim 16, further comprising a step of forming said gate layer for said trench type insulated gate semiconductor element and a gate layer for said lateral type insulated gate semiconductor element in an identical process.

18. An insulated gate type semiconductor device comprising:

a trench type insulated gate semiconductor element;

a diode concerning a gate-protection of said trench type insulated gate semiconductor element,

said trench type insulated gate semiconductor element including plural grooves provided in a main surface of a semiconductor layer in a semiconductor substrate, gate layers connected to a first electrode which are provided inside and outside of said grooves through a gate insulating film, a second electrode provided on a surface of said semiconductor layer opposite to said main surface, and a diffusion layer connected to a third electrode, said diffusion layer being provided between said gate layers,

said gate layers having gate layer regions on said grooves and another gate layer regions extending to said outside of said groove,

said first electrode being connected to said first electrode on said another gate layer regions extending to said outside of said groove,

said diode being provided on an insulating film on said main surface of said semiconductor layer in said semiconductor layer,

said diode having film thickness smaller than that of said another gate layer regions extending to said outside of said groove for connection of said first electrode and said gate layer.

19. An insulated gate type semiconductor device as in claim 18, wherein said trench type insulated semiconductor element is a MOSFET, depth of said MOSFET'"'"'s source diffusion layer connected to said MOSFET'"'"'s source electrode is not greater than depth of said source diffusion layer of said lateral type insulated gate semiconductor element.

20. An insulated gate type semiconductor device as in one of claim 18, wherein said trench type insulated semiconductor element is an IGBT, depth of said emitter diffusion layer is not greater than depth of said source diffusion layer of said lateral type insulated gate semiconductor element.

21. A method of manufacturing an insulated gate type semiconductor device as in claim 18, comprising:

forming plural grooves in a main surface of a semiconductor layer in said semiconductor substrate;

forming a gate layer for connection of said first electrode inside of said grooves through a gate insulating film;

forming a body diffusion layer between each said gate layer; and

then forming a diffusion layer for connection of said third electrode.

22. A method of manufacturing an insulated gate type semiconductor device as in claim 18 comprising:

forming plural grooves in a main surface of a semiconductor layer in said semiconductor substrate;

forming a gate layer for connection of said first electrode inside of said grooves through a gate insulating film;

forming a body diffusion layer between each said gate layer; and

then forming a diffusion layer for connection of said third electrode and a source diffusion layer for said lateral type insulated gate semiconductor element in an identical process.

23. A method of manufacturing an insulated gate type semiconductor device as in claim 18 comprising:

forming plural grooves in a main surface of a semiconductor layer in said semiconductor substrate;

forming a gate layer for connection of said first electrode inside of said grooves through a gate insulating film;

forming a body diffusion layer between each said gate layer; and

then forming a diffusion layer for connection of said third electrode and a cathode or anode layer for said diode in an identical process.