Crest factor compensated driver

• US 6,323,686 B1
• Filed: 07/25/2000
• Issued: 11/27/2001
• Est. Priority Date: 07/30/1999
• Status: Expired due to Term

• Current Assignee: Ciena Corporation
• Original Assignee: Catena Networks, Inc. (Ciena Corporation)
• Inventors: Bisson, Robert, Tremblay, Francois
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/625,571
• Time in Patent Office: 490 Days
• Field of Search: 326/21, 326/22, 326/26, 326/29, 326/30, 326/82, 326/83, 326/86, 379/414-417, 379/351, 379/394, 379/398
• US Class Current: 326/82
• CPC Class Codes: H04B 1/74 for increasing reliability, e.g. using redundant or spare channels or apparatus replacing by standby devices for amplifiers H03F1/52, H03F1/542
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: H04L 27/2614 Peak power aspects

Abstract

A telephone line feed circuit for use with a telecommunication line has dual drivers with differing ratio transformer taps and a sensing circuit so that under normal drive conditions a first driver supplies substantially all power through a first transformer of a first turns ratio under normal in put signal conditions and a second driver supplies substantially all power through a second transformer of a second turns ratio under high crest factor input signal conditions.

Claims

1. A telephone line feed circuit for use with a telecommunication line, comprising:

a) a first driver circuit having an output connected via a first transformer having a first turns ratio to a tip terminal and to a ring terminal of said telecommunication line;

b) a second driver circuit having an output connected via a second transformer having a second turns ratio to the tip terminal and the ring terminal of said telecommunication line; and

c) a switching circuit arranged to provide an input signal to said driver circuits so that substantially all of the drive power is provided by said first driver circuit under normal input signal conditions and substantially all of the drive power is provided by the second driver circuit under high crest factor input signal conditions, the turns ratios of the first transformer and of the second transformer being selected such that signals driven onto the line via said first driver circuit and said second driver circuit are not clipped.

2. A circuit as defined in claim 1, said driver circuits being operative to receive signals from an integrated POTS and xDSL line card.

3. A circuit as defined in claim 1, said driver circuit including an active impedance synthesis circuit for generating line impedance for DSL signals.

4. A circuit as defined in claim 3, wherein said impedance synthesis circuit is operative to synthesize an impedance by sensing a current in the telecommunication line and driving a voltage source with a corresponding voltage.

5. A circuit as defined in claim 4, wherein said current being sensed is on the secondary side of one of said transformers.

6. A circuit as defined in claim 4, wherein said current being sensed is on the primary side of one of said transformers.

7. A circuit as defined in claim 5, including a sense resistor coupled in series in said line.

8. A circuit as defined in claim 6, including a sense resistor coupled in series in said line.

9. A circuit as defined in claim 5, including a sense transformer coupled in series in said line.

10. A circuit as defined in claim 6, including a sense transformer coupled in series in said line.

11. A circuit as defined in claim 3, wherein said impedance synthesis circuit is operative to synthesize an impedance by sensing a voltage on the telecommunication line and driving a current source with a corresponding current.

12. A circuit as defined in claim 11, wherein said voltage being sensed is on the secondary side of one of said first and second transformers.

13. A circuit as defined in claim 11, wherein said voltage being sensed is on the primary side of one of said first and second transformers.

14. A circuit as defined in claim 1 wherein said first driver circuit is switched to a high impedance state from a low impedance state while said second driver circuit is providing power under high crest factor signal input conditions;

and

wherein said second driver circuit is switched to a high impedance state from a low impedance state while said first driver circuit is providing power low signal excursion conditions.

15. In telephone line feed circuit for use with a telecommunication line, said line feed circuit including a first driver circuit having an output connected via a first transformer having a first turns ratio to a tip terminal and to a ring terminal of said telecommunication line, a second driver circuit having an output connected via a second transforner having a second turns ratio to the tip terminal and the ring terminal of said telecommunication line, and a switching circuit, a method for inhibiting signal clipping comprising:

providing substantially all of an input signal at normal input signal conditions by said first driver circuit; and

providing substantially all of said input signal under high crest factor input signal conditions by said second driver circuit, wherein the turns ratios of the first transformer and the second transformers being selected such that the signal driven onto the line is not clipped.

16. The method according to claim 15 further including actively synthesizing impedance in said first and second driver circuits for generating line impedance for DSL signals.

17. The method according to claim 16 wherein said impedance synthesizing step includes synthesizing an impedance by sensing a current in the telecommunication line and driving a voltage source with a corresponding voltage.

18. The method according to claim 16 wherein said impedance synthesizing step includes synthesizing an impedance by sensing a voltage on the telecommunication line and driving a current source with a corresponding current.

19. The method according to claim 16

wherein said first driver circuit is switched to a high impedance state from a low impedance state while said second driver circuit is providing power under high crest factor signal input conditions; and

wherein said second driver circuit is switched to a high impedance state from a low impedance state while said first driver circuit is providing power.