Substrate voltage detector

• US 6,323,721 B1
• Filed: 03/01/2000
• Issued: 11/27/2001
• Est. Priority Date: 07/26/1996
• Status: Expired due to Term

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Townsend and Townsend and Crew LLP (Kilpatrick Townsend & Stockton LLP)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US09/516,879
• Time in Patent Office: 636 Days
• Field of Search: 327/541, 327/543, 327/537, 327/540, 327/535
• US Class Current: 327/535
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/071 adapted to generate a negative voltage output from a positive voltage source
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator. When the substrate voltage is above the desired level, the comparator generates a pump activating signals to a pump signal generator which, in turn, generates the necessary signal to cause the charge pump to operate.

Claims

1. A power supply circuit coupled to a first voltage, a second voltage, and a control voltage, said power supply circuit comprising:

a plurality of MOS transistors serially coupled between the first voltage and the second voltage, wherein said plurality of MOS transistors comprises both PMOS and NMOS transistors,

wherein one of said plurality of MOS transistors is switchable in response to the control voltage, has a first current flowing terminal coupled to another of the plurality of MOS transistors, a second current flowing terminal coupled to the second voltage, and a control terminal coupled to the control voltage, and

wherein the power supply circuit is configured to generate a third voltage at an output node when the control voltage is above a selected value and to generate a fourth voltage at the output node when the control voltage is below the selected value.

2. The power supply according to claim 1 wherein the first voltage is higher than the second voltage.

3. The power supply circuit according to claim 1 wherein the first voltage is a high voltage and the second voltage is a ground voltage.

4. The power supply circuit according to claim 3 wherein the control voltage is a substrate voltage of a substrate.

5. The power supply circuit according to claim 1 wherein the plurality of MOS transistors comprises:

a first PMOS transistor having a source terminal coupled to the first voltage, a drain terminal coupled to the output node, and a gate terminal coupled to the second voltage;

two diode-connected NMOS transistors serially coupled between the output node and a second node;

a diode-connected PMOS transistor coupled between the second node and a third node;

a second PMOS transistor having a source terminal coupled to the N well of said second PMOS transistor and to the third node, a gate terminal coupled to the control voltage, and a drain terminal coupled to the second voltage, said second PMOS transistor comprising the switchable MOS transistor.

6. The power supply circuit according to claim 1 wherein the output node is coupled to a first PMOS transistor and to a first NMOS transistor, wherein the first PMOS transistor and the first NMOS transistor are two of the plurality of serially-coupled MOS transistors.

7. The power supply circuit according to claim 1 wherein the plurality of MOS transistors comprises at least two NMOS transistors, and wherein each NMOS transistor is diode-connected.

8. The power supply circuit according to claim 1 wherein the switchable MOS transistor is a PMOS transistor.