Apparatus for translating a voltage

• US 6,323,722 B1
• Filed: 03/01/2000
• Issued: 11/27/2001
• Est. Priority Date: 07/29/1996
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Townsend and Townsend and Crew LLP (Kilpatrick Townsend & Stockton LLP)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US09/516,399
• Time in Patent Office: 636 Days
• Field of Search: 327/536, 327/589, 327/534, 327/535, 327/390, 327/537
• US Class Current: 327/536
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/071 adapted to generate a negative voltage output from a positive voltage source
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator. When the substrate voltage is above the desired level, the comparator generates a pump activating signals to a pump signal generator which, in turn, generates the necessary signal to cause the charge pump to operate.

Claims

1. An apparatus for translating a substrate voltage comprising:

a capacitance having a first input terminal and a second input terminal;

a first switch coupled between a first voltage and one of the first and second input terminals;

a second switch coupled between a substrate voltage and the other of the first and second input terminals, wherein the second switch comprises an NMOS transistor;

switch control means, coupled to the first and second switches, for closing the first and second switches so that the capacitance charges to a difference voltage between the first and second input terminals approximately equal to the difference between the first voltage and the substrate voltage;

wherein the switch control means opens the first and second switches after the capacitance charges to the difference voltage, and

wherein the switch control means couples a gate terminal of the NMOS transistor to the substrate voltage while the capacitance charges to the difference voltage, and wherein the switch control means couples the gate terminal of the NMOS transistor to a second voltage after the capacitance charges to the difference voltage, wherein the second voltage is a voltage that differs from the substrate voltage by an amount of voltage substantially equal to the first voltage;

a third switch coupled between a third voltage and one of the first and second input terminals; and

wherein the switch control means is coupled to the third switch and closes the third switch after the capacitance charges to the difference voltage so that the one of the first and second input terminals coupled to the third voltage has a voltage equal to the third voltage and the voltage at the other of the first and second input terminals changes by an amount approximately equal to the difference between the first voltage and the third voltage.

2. The voltage translator according to claim 1 wherein the first switch is coupled to the first input terminal, wherein the second switch is coupled to the second input terminal, and wherein the third switch is coupled to the first input terminal.

3. The voltage translator according to claim 2 wherein the third voltage is a positive voltage relative to the first voltage.

4. The voltage translator according to claim 3 wherein the difference between the first voltage and the third voltage is greater than the difference between the first voltage and the substrate voltage.

5. The voltage translator according to claim 4 wherein the substrate voltage is a negative voltage relative to the first voltage.

6. The voltage translator according to claim 5 wherein the first voltage is a ground potential.

7. An apparatus for translating an input voltage comprising:

a capacitance having a first terminal and a second terminal;

a first switch coupled between a first voltage and one of the first and second terminals;

a second switch coupled between the input voltage and the other of the first and second terminals, wherein the second switch comprises an NMOS transistor;

a third switch coupled between a second voltage and one of the first and second terminals; and

a switch control circuit, coupled to the first, second, and third switches;

wherein the switch control circuit closes the first and second switches so that the capacitance charges to a difference voltage between the first and second terminals approximately equal to the difference between the first voltage and the input voltage, and wherein the switch control circuit opens the first and second switches after the capacitance charges to the difference voltage;

wherein the switch control circuit couples a gate terminal of the NMOS transistor to the input voltage while the capacitance charges to the difference voltage, and wherein the switch control circuit couples the gate terminal of the NMOS transistor to a third voltage after the capacitance charges to the difference voltage, said third voltage differing from the input voltage by an amount of voltage substantially equal to the first voltage; and

wherein the switch control circuit closes the third switch after the capacitance charges to the difference voltage so that the one of the first and second terminals coupled to the second voltage has a voltage equal to the second voltage and the voltage at the other of the first and second terminals changes by an amount approximately equal to the difference between the first voltage and the second voltage.

8. The voltage translator of claim 7 wherein the input voltage is a substrate voltage of a substrate.

9. The voltage translator of claim 7 wherein the first switch is coupled to the first terminal, wherein the second switch is coupled to the second terminal, and wherein the third switch is coupled to the first terminal.

10. The voltage translator of claim 9 wherein the second voltage is a positive voltage relative to the first voltage.

11. The voltage translator of claim 10 wherein the difference between the first voltage and the second voltage is greater than the difference between the first voltage and the input voltage.

12. The voltage translator of claim 11 wherein the input voltage is a negative voltage relative to the first voltage.

13. The voltage translator of claim 12 wherein the first voltage is a ground potential.

14. A charge pump comprising:

a capacitance having a first terminal and a second terminal; and

a switching circuit coupled to the capacitance,

wherein the switching circuit is configured such that, at a first time, the switching circuit couples the first terminal of the capacitance to a high voltage and couples the second terminal of the capacitance to a low voltage, and at a second time, couples the first terminal of the capacitance to the low voltage and couples the second terminal of the capacitance to an output voltage of an output node,

wherein the switching circuit comprises an NMOS transistor for coupling the second terminal of the capacitance to the output voltage, and

wherein, at substantially the first time, a gate terminal of the NMOS transistor is driven to the output voltage, and at substantially the second time, the gate terminal of the NMOS transistor is driven to a first voltage greater than the output voltage by an amount of voltage substantially equal to a difference between the high voltage and the low voltage.

15. The charge pump of claim 14 wherein the high voltage is substantially equal to a positive power supply voltage applied to the charge pump circuit, and the low voltage is substantially equal to ground.

16. The charge pump of claim 15 wherein the output voltage is a substrate voltage of a substrate.

20. The charge pump of claim 16 wherein the gate terminal of the NMOS transistor is coupled to a second capacitance.

21. The charge pump of claim 20 wherein the switch control circuitry is configured such that the charge pump reaches an equilibrium operating condition wherein the amount of charge transferred from the substrate in order to drive the voltage at the gate terminal of the NMOS transistor between the output voltage and the first voltage is substantially equal to zero.

17. A charge pump comprising:

a capacitance having a first terminal and a second terminal;

a first switch coupled between the first terminal of the capacitance and a high voltage;

a second switch coupled between the first terminal of the capacitance and a low voltage;

a third switch coupled between the second terminal of the capacitance and the low voltage;

a fourth switch coupled between the second terminal of the capacitance and an output voltage of an output node; and

switch control circuitry coupled to the first, second, third and fourth switches,

wherein the fourth switch comprises an NMOS transistor having a first source/drain terminal coupled to the second terminal of the capacitance, a second source/drain terminal coupled to the output voltage, and a gate terminal coupled to a voltage generating circuit, and

wherein the voltage generating circuit is configured to couple the gate terminal of the NMOS transistor to the output voltage at a first time, and to couple the gate terminal of the NMOS transistor to a first voltage at a second time, wherein the first voltage is greater than the output voltage by a voltage substantially equal to the high voltage.

18. The charge pump of claim 17 wherein the switch control circuitry is configured to turn on the first switch and the third switch, and turn off the second switch and the fourth switch, at substantially the first time, and

to turn on the second switch and the fourth switch, and turn off the first switch and the third switch, at substantially the second time.

19. The charge pump of claim 18 wherein the output voltage is a substrate voltage of a substrate.