Liquid crystal display device and method for fabricating thereof
First Claim
Patent Images
1. A display device comprising:
- a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
a plurality of thin film transistors over said substrate, each thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
a first interlayer insulating film including silicon over said thin film transistors;
a second interlayer insulating film comprising organic resin over said first interlayer insulating film;
a plurality of pixel electrodes over said second interlayer insulating film, each connecting to a drain electrode of the corresponding thin film transistor;
an opposed substrate comprising an opposed electrode on a surface thereof; and
at least one spacer and a liquid crystal material, both interposed between said substrate and said opposed substrate, wherein a pixel pitch of said pixel area is 40 μ
m or less, and wherein a thickness of said spacer in a direction vertical to said a substrate and the opposed substrate is 4 μ
m or less.
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Accused Products
Abstract
To provide a technology for fabricating a high image quality liquid crystal display device, a set range of a cell gap for holding a liquid crystal layer is limited in accordance with a distance of a pixel pitch in which specifically, the cell gap is set to be a distance of one tenth of the pixel pitch, whereby the high image quality liquid crystal display device with no occurrence of image display failure caused by disturbances of an electric field such as disclination, can be realized.
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Citations
66 Claims
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1. A display device comprising:
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a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
a plurality of thin film transistors over said substrate, each thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
a first interlayer insulating film including silicon over said thin film transistors;
a second interlayer insulating film comprising organic resin over said first interlayer insulating film;
a plurality of pixel electrodes over said second interlayer insulating film, each connecting to a drain electrode of the corresponding thin film transistor;
an opposed substrate comprising an opposed electrode on a surface thereof; and
at least one spacer and a liquid crystal material, both interposed between said substrate and said opposed substrate, wherein a pixel pitch of said pixel area is 40 μ
m or less, andwherein a thickness of said spacer in a direction vertical to said a substrate and the opposed substrate is 4 μ
m or less.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of fabricating a display device comprising the steps of:
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forming a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
forming a plurality of thin film transistors over said substrate, each thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
forming a first interlayer insulating film including silicon over said thin film transistors;
forming a second interlayer film comprising organic resin over said first interlayer insulating film;
forming a plurality of pixel electrodes over said second interlayer insulating film, each connecting to a drain electrode of the corresponding thin film transistor;
forming an opposed substrate comprising an opposed electrode on a surface thereof; and
providing a liquid crystal material between said substrate and said opposed substrate, wherein a pixel pitch of said pixel area is 40 μ
m or less,wherein an interval between said substrate and said opposed substrate is 4 μ
m or less, andwherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μ
m or less.- View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A display device comprising:
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a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
a plurality of thin film transistors over said substrate, each of said thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
a first interlayer insulating film including silicon over said thin film transistors;
a second interlayer insulating film comprising organic resin over said first interlayer insulating film;
a plurality of pixel electrodes over said second interlayer insulating film, each pixel electrode formed over the corresponding thin film transistor and connected to a drain electrode of said thin film transistor;
an opposed substrate comprising at least an opposed electrode on a surface thereof; and
a liquid crystal material interposed between said substrate and said opposed substrate, wherein an interval between said substrate and said opposed substrate is 4 μ
m or less, andwherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μ
m or less.- View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A display device comprising:
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a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
a plurality of thin film transistors formed over said substrate, each of said thin film transistors arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
a first interlayer insulating film including silicon formed over said thin film transistors;
a second interlayer insulating film comprising organic resin formed over said first interlayer insulating film;
a plurality of black matrices, each black matrix formed over a corresponding thin film transistor;
a plurality of pixel electrodes, each pixel electrode formed over said second interlayer insulating film and connected to a drain electrode of said thin film transistor;
an opposed substrate comprising at least an opposed electrode on a surface thereof; and
a liquid crystal material interposed between said active matrix substrate and said opposed substrate, and wherein an interval between said substrate and said opposed substrate is 4 μ
m or less, andwherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μ
m or less.- View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A display device comprising:
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a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
a plurality of thin film transistors over said substrate, each thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
a first interlayer insulating film including silicon over said thin film transistors;
a second interlayer insulating film comprising organic resin over said first interlayer insulating film;
a plurality of pixel electrodes over said second interlayer insulating film, each pixel electrode connecting to a drain electrode of the corresponding thin film transistor;
an opposed substrate comprising at least an opposed electrode on a surface thereof; and
a liquid crystal material interposed between said substrate and said opposed substrate, wherein a pixel pitch of said pixel area is 40 μ
m or less, andwherein an interval between said substrate and said opposed substrate is 4 μ
m or less.- View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50)
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51. An electric device comprising:
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a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
a plurality of switching elements over said substrate, each switching element arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
a plurality of pixel electrodes, each pixel electrode connecting to the corresponding switching element;
an opposed substrate comprising at least an opposed electrode on a surface thereof; and
a liquid crystal material interposed between said substrate and said opposed substrate;
wherein a pixel pitch of said pixel area is 40 μ
m or less,wherein a thickness of said spacer in a direction vertical to said a substrate and the opposed substrate is 4 μ
m or less, andwherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μ
m or less.- View Dependent Claims (52, 53, 54, 55, 56, 57, 58)
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59. An electric device comprising:
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a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
a plurality of switching elements over said substrate, each of said switching element arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
a first interlayer insulating film including silicon over said switching elements;
a second interlayer insulating film comprising organic resin over said first interlayer insulating film;
a plurality of pixel electrodes over said second interlayer insulating film, each pixel electrode formed over the corresponding switching element and connected to a drain electrode of said switching element;
an opposed substrate comprising at least an opposed electrode on a surface thereof; and
a liquid crystal material interposed between said substrate and said opposed substrate, wherein an interval between said substrate and said opposed substrate is 4 μ
m or less, andwherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μ
m or less.- View Dependent Claims (60, 61, 62, 63, 64, 65, 66)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsFukunaga, Takeshi, Zhang, Hongyong
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Primary Examiner(s)Ton, Toan
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Application NumberUS08/835,725Time in Patent Office1,691 DaysField of Search349/155, 349/158, 349/44, 349/156, 349/150, 349/153US Class Current349/155CPC Class CodesG02F 1/133388 with constructional differe...G02F 1/13392 spacers dispersed on the ce...G02F 1/1341 Filling or closing of cellsG02F 1/1362 Active matrix addressed cel...G02F 1/136209 Light shielding layers, e.g...G02F 1/136227 Through-hole connection of ...
