Memory device having a variable data output length

• US 6,324,120 B2
• Filed: 02/08/2001
• Issued: 11/27/2001
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Toshiba Storage Device Corp (Toshiba Corporation)
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/779,296
• Publication Number:
  US 20010009531A1
• Time in Patent Office: 292 Days
• Field of Search: 365/233, 365/194, 365/233.5, 365/238.5
• US Class Current: 365/233.12
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing block size information to the memory device, synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes issuing a first read request to the memory device, wherein the memory device receives the first read request synchronously with respect to a transition of the external clock signal.

Claims

1. A method of operation of a synchronous memory device, wherein the memory device includes an array of memory cells, the method of operation comprises:

receiving an external clock signal;

receiving block size information, wherein the block size information defines an amount of data to be output by the memory device in response to a first operation code;

sampling the first operation code synchronously with respect to the external clock signal wherein the first operation code instructs the memory device to perform a read operation; and

outputting the amount of data in response to the first operation code.

2. The method of claim 1 wherein the block size information also defines an amount of data to be input by the memory device, wherein the amount of data is input in response to a second operation code, and wherein the second operation code instructs the memory device to perform a write operation, the method further including:

sampling the second operation code synchronously with respect to a transition of the external clock signal; and

inputting the amount of data in response to the second operation code.

3. The method of claim 2 wherein a first portion of the amount of data is sampled, in response to the second operation code after a delay time transpires.

4. The method of claim 1 wherein the amount of data is output synchronously with respect to the external clock signal.

5. The method of claim 4 wherein a first portion of the amount of data is output synchronously with respect to a rising edge transition of the external clock signal and a second portion of the amount of data is output synchronously with respect to a falling edge transition of the external clock signal.

6. The method of claim 1 wherein the memory device samples the block size information synchronously with respect to the external clock signal.

7. The method of claim 1 wherein the first operation code includes precharge information.

8. The method of claim 1 wherein the first operation code is included in a request packet.

9. The method of claim 8 wherein the block size information and the first operation code are both included in the same request packet.

10. The method of claim 8 wherein the request packet includes address information.

11. The method of claim 1 wherein the block size information is an encoded value and wherein the block size information is sampled synchronously with respect to a rising or falling edge of the external clock signal.

12. The method of claim 1 further including:

receiving a value which is representative of a number of clock cycles of the external clock signal to transpire before the memory device outputs the data; and

receiving a third operation code wherein the third operation code instructs the memory device to store the value in a programmable register on the memory device.

13. The method of claim 12 wherein the memory device outputs the data on an external bus after the number of clock cycles of the external clock signal transpire.

14. The method of claim 12 wherein the external bus includes a plurality of signal lines to multiplex control information, address information, and the amount of data.

15. A method of controlling a synchronous memory device by a controller, wherein the memory device includes an array of memory cells, the method of controlling the memory device comprises:

issuing block size information to the memory device synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device; and

issuing a first operation code to the memory device synchronously with respect to the external clock signal, wherein the first operation code instructs the memory device to perform a read operation.

16. The method of claim 15 further including receiving the amount of data from the memory device.

17. The method of claim 15 further including providing a binary value to the memory device, wherein the binary value is representative of a number of clock cycles of the external clock signal to transpire before the memory device outputs the amount of data in response to the first operation code.

18. The method of claim 17 further including providing a second operation code to the memory device, wherein the second operation code instructs the memory device to store the binary value in a register on the memory device.

19. The method of claim 15 wherein the first operation code is issued synchronously with respect to a rising or falling edge transition of the external clock signal.

20. The method of claim 15 wherein the first operation code includes precharge information.

21. The method of claim 15 wherein the first operation code is provided to the memory device via an external bus.

22. The method of claim 21 wherein the external bus includes a plurality of signal lines to multiplex control information, address information and data.

23. The method of claim 15 wherein the block size information and the first operation code are both included in a request packet.

24. The method of claim 15 further including providing address information to the memory device.

25. The method of claim 15 wherein the block size information is a binary code.

26. A synchronous dynamic random access memory device having at least one memory section including a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive an external clock signal;

input receiver circuitry, including a first plurality of input receivers to sample block size information synchronously with respect to the external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a first operation code; and

a plurality of output drivers to output the amount of data in response to the first operation code.

27. The memory device of claim 26 wherein the amount of data is output synchronously with respect to the external clock signal.

28. The memory device of claim 27 wherein a first portion of the amount of data is output synchronously with respect to a rising edge transition of the external clock signal and a second portion of the amount of data is output synchronously with respect to a falling edge transition of the external clock signal.

29. The memory device of claim 26 wherein the input receiver circuitry samples the first operation code synchronously with respect to the external clock signal.

30. The memory device of claim 29 wherein the input receiver circuitry includes a second plurality of input receivers to receive the first operation code.

31. The memory device of claim 30 wherein the first and second plurality of input receivers are coupled to an external bus.

32. The memory device of claim 31 wherein the external bus includes a plurality of signal lines to multiplex control information, address information and the data.

33. The memory device of claim 29 wherein the first operation code includes precharge information.

34. The memory device of claim 26 further including a programmable register to store a value which is representative of a number of clock cycles of the external clock signal to transpire before the memory device outputs the data in response to the first operation code.

35. The memory device of claim 26 wherein the block size information further defines an amount of data to be input by the memory device in response to a second operation code, wherein the second operation code instructs the memory device to perform a write operation, and wherein the input receiver circuitry receives the amount of data in response to the second operation code.

36. The memory device of claim 35 wherein the input receiver circuitry and the plurality of output drivers are coupled to an external bus.

37. The memory device of claim 36 wherein the external bus includes a plurality of signal lines to multiplex control information, address information and the amount of data to be input.

38. The memory device of claim 26 further including delay lock loop circuitry coupled to the clock receiver circuitry to generate an internal clock signal, wherein the plurality of output drivers output data in response to the internal clock signal.

39. The method of claim 26 wherein the block size information is a binary code.