Large capacity, multiclass core ATM switch architecture
DCFirst Claim
1. An ATM switch capable of supporting streams of different classes having various quality of service requirements, comprising:
- a core switch comprising;
a TDM bus;
a plurality of input ports connected to said TDM bus;
a plurality of output buffers connected to said TDM bus;
a plurality of output ports connected to respective output buffers; and
a multicast output buffer connected to each of said output ports;
a plurality of input modules connected to input side of said core switch, each of said input modules comprising;
a plurality of output port planes corresponding to the number of said output ports, each of said output port planes having a plurality of input buffers;
an input module scheduler for scheduling cells in said input buffers;
a plurality of output modules connected to output side of said core switch, each of said output modules comprising;
a plurality of output line planes, each having a plurality of output line buffers coupled to an output line;
an output module scheduler for scheduling cells in said output buffers.
8 Assignments
Litigations
0 Petitions
Accused Products
Abstract
A large capacity ATM core switch architecture is disclosed, which supports multiple traffic classes and quality-of-service (QoS) guarantees. The switch supports both real-time traffic classes with strict QoS requirements, e.g., CBR and VBR, and non-real-time traffic classes with less stringent requirements, e.g., ABR and UBR. The architecture also accommodates real-time and non-real-time multicast flows in an efficient manner. The switch consists of a high-speed core module that interconnects input/output modules with large buffers and intelligent scheduling/buffer management mechanisms. The scheduling can be implemented using a novel dynamic rate control, which controls internal congestion and achieves fair throughput performance among competing flows at switch bottlenecks. In the dynamic rate control scheme, flows are rate-controlled according to congestion information observed at bottleneck points within the switch. Each switch flow is guaranteed a minimum service rate plus a dynamic rate component which distributes any unused bandwidth in a fair manner.
-
Citations
23 Claims
-
1. An ATM switch capable of supporting streams of different classes having various quality of service requirements, comprising:
-
a core switch comprising;
a TDM bus;
a plurality of input ports connected to said TDM bus;
a plurality of output buffers connected to said TDM bus;
a plurality of output ports connected to respective output buffers; and
a multicast output buffer connected to each of said output ports;
a plurality of input modules connected to input side of said core switch, each of said input modules comprising;
a plurality of output port planes corresponding to the number of said output ports, each of said output port planes having a plurality of input buffers;
an input module scheduler for scheduling cells in said input buffers;
a plurality of output modules connected to output side of said core switch, each of said output modules comprising;
a plurality of output line planes, each having a plurality of output line buffers coupled to an output line;
an output module scheduler for scheduling cells in said output buffers. - View Dependent Claims (2, 3, 4, 5, 6)
connection admission control for issuing queue timestamps for each cell in said plurality of input buffers;
a timer issuing a current time; and
,wherein said input module scheduler further comprises a comparator for comparing said queue timestamps to said current time, and scheduling eligibility for service each of said cells having queue timestamp equal to current time.
-
-
4. The ATM switch of claim 3, wherein each of said input module scheduler and output module scheduler further comprises:
-
a timestamp storage unit for storing the queue timestamps and providing said queue timestamps to said comparator;
a virtual rate shaping unit connected to said comparator for shaping transmission rate of cells eligible for service;
a plurality of virtual queue counters for counting the number of cells eligible for service;
a service scheduling unit for scheduling cells eligible for service;
a compute engine for dynamically updating the timestamps.
-
-
5. The ATM switch of claim 4, further comprising a rate feedback from said output modules to said input modules.
-
6. The ATM switch of claim 1, wherein said plurality of output buffers of said core switch are designated real-time output buffers and wherein said core switch further comprises:
-
a plurality of non-real-time output buffers corresponding to the number of real-time output buffers and each connected to one of said output ports;
a non-real-time multicast buffer connected to each of said output ports.
-
-
7. An ATM switch capable of supporting cell streams of different classes having various quality of service requirements, comprising:
-
a core switch comprising;
a TDM bus;
a plurality of input ports connected to said TDM bus;
a plurality of output buffers connected to said TDM bus;
a plurality of output ports connected to respective output buffers; and
a multicast output buffer connected to each of said output ports;
a plurality of output modules connected to output side of said core switch, each of said output modules having a plurality of output lines and comprising;
a plurality of output line planes, each having a plurality of output line buffers coupled to said output lines;
an output module scheduler for scheduling cells in said output buffers;
a plurality of input modules connected to input side of said core switch, each of said input modules comprising;
a plurality of output port planes corresponding to the number of said output ports, each of said output port planes having a plurality of output line planes corresponding to the number of said output lines, each of said output line planes having a plurality of input buffers;
an input module scheduler for scheduling cells in said input buffers. - View Dependent Claims (8, 9, 10, 11, 12)
connection admission control for issuing queue timestamps for each cell in said plurality of input buffers;
a timer issuing a current time; and
,wherein said input module scheduler further comprises a comparator for comparing said queue timestamps to said current time, and scheduling eligibility for service each of said cells having queue timestamp equal to current time.
-
-
10. The ATM switch of claim 9, wherein each of said input module scheduler and output module scheduler further comprises:
-
a timestamp storage unit for storing the queue timestamps and providing said queue timestamps to said comparator;
a virtual rate shaping unit connected to said comparator for shaping transmission rate of cells eligible for service;
a plurality of virtual queue counters for counting the number of cells eligible for service;
a service scheduling unit for scheduling cells eligible for service;
a compute engine for dynamically updating the timestamps.
-
-
11. The ATM switch of claim 10, further comprising a rate feedback from said output modules to said input modules.
-
12. The ATM switch of claim 7, wherein said plurality of output buffers of said core switch are designated real-time output buffers and wherein said core switch further comprises:
-
a plurality of non-real-time output buffers corresponding to the number of real-time output buffers and each connected to one of said output ports;
a non-real-time multicast buffer connected to each of said output ports.
-
-
13. An ATM switch capable of supporting streams of different classes having various quality of service requirements, comprising:
-
a core switch comprising;
a TDM bus;
a plurality of input ports connected to said TDM bus;
a plurality of output buffers connected to said TDM bus;
a plurality of output ports connected to respective output buffers;
a plurality of input modules connected to input side of said core switch, each of said input modules comprising;
a plurality of input buffers;
a connection admission control assigning a minimum guaranteed rate and an excess share weight for each of said input buffers;
an input module scheduler for scheduling cells in said input buffers according to a rate composed of said minimum guaranteed rate and a share of the available unused bandwidth, said share being proportional to the excess share weight. - View Dependent Claims (14, 15)
-
-
16. A tripled buffered ATM switch capable of supporting streams of different classes having various quality of service requirements, comprising:
-
a plurality of input buffers for queuing incoming cell streams;
a plurality of core buffers receiving queued cells of said cell streams from said input buffers and providing said queued cell to respective output ports;
a plurality of output buffers receiving said queued cells from said output ports and providing said queued cell to respective output lines;
a scheduler for scheduling transmission of said queued cells from said input buffers;
a first feedback loop from said core buffers to said scheduler, for transmission of load information of said core buffers to said scheduler;
a second feedback loop from said output buffers to said scheduler, for transmission of load information of said output buffers to said scheduler;
wherein said scheduler schedules transmission of said queued cells from said input module according to information received from said first and second feedback loops. - View Dependent Claims (17, 18, 19)
-
-
20. A scheduler for an ATM switch, comprising:
-
a first memory for storing cells timestamps assigned to cells in queues to be scheduled;
a second memory for storing actual queue load;
a third memory for storing cells in virtual queues;
a current time generator generating current time;
a plurality of comparators for comparing the cells timestamps to current time and designating cells having cell timestamps≧
current time as eligible for service;
a virtual rate selector for assigning cells from said eligible cells to said virtual queues;
a service scheduling selector which selects queues for service from said virtual queues;
a compute engine for scheduling and rescheduling cells in said first memory.
-
-
21. A buffer, comprising:
a first monitoring circuit for monitoring a load level in said buffer and for generating a shape signal when said load level reaches a first threshold, so as to cause input to said buffer to be reduced to a minimum level, and further for generating a stop signal when said load level reaches a second threshold, so as to halt any input to said buffer. - View Dependent Claims (22)
-
23. A scheduler for an ATM switch, comprising:
-
a first memory for storing queue timestamps assigned to queues to be scheduled;
a second memory for storing actual queue load;
a third memory for storing cells in virtual queues;
a current time generator generating current time;
a plurality of comparators for comparing the queue timestamps to current time and designating queues having cell timestamps≦
current timestamp as eligible for service;
a virtual rate selector for assigning cells from said eligible cells to said virtual queues;
a service scheduling selector which selects queues for service from said virtual queues;
a compute engine for scheduling and rescheduling cells in said first memory.
-
Specification