Method for optimizing cost of manufacturing memory arrays

• US 6,324,436 B1
• Filed: 09/14/1998
• Issued: 11/27/2001
• Est. Priority Date: 09/14/1998
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Moresco, Larry L.
• Primary Examiner(s): Grant, William
• Assistant Examiner(s): Hartman, Jr., Ronald D
• Application Number:
  US09/152,739
• Time in Patent Office: 1,170 Days
• Field of Search: 700/36, 700/110, 700/121, 714/755, 716/3
• US Class Current: 700/36
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06Q 10/04 Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem" market predictions or forecasting for commercial activities G06Q30/0202

Abstract

A method of determining the most cost effective manner in which to provide a given number of memory or logic gates for a particular application. The method takes into consideration both the cost per memory bit of fabricating memory cells on a semiconductor chip as a function of the number of memory cells on the chip (i.e, the chip size), and the costs of assembling multiple memory chips into a larger memory device using different assembly and packaging configurations. By considering the fabrication and packaging costs together, the most economically efficient combination of memory chip size and packaging method to produce a desired memory capacity can be determined.

Claims

1. A method of manufacturing a memory array, comprising:

selecting a first value of a memory cell capacity of a memory die;

determining a cost to fabricate the memory die having the selected memory cell capacity;

selecting an assembly and packaging method for assembling a plurality of memory die having the selected memory cell capacity into the memory array;

determining a cost to assemble the plurality of memory die into the memory array using the selected assembly and packaging method;

determining an overall cost of manufacturing the memory array by combining the costs of fabricating the plurality of memory die and assembling and packaging the die;

selecting a second value of a memory cell capacity of a memory die; and

repeating the steps of the method required to determine an overall cost to manufacture the memory array from a plurality of memory die having a memory cell capacity equal to the second value.

2. The method of claim 1, further comprising the step of:

manufacturing the memory array using memory die having the memory cell capacity value which results in a lower overall manufacturing cost.

3. The method of claim 1, wherein the step of determining a cost to fabricate the memory die further comprises:

selecting a fabrication process flow for fabricating the memory die; and

selecting a yield function corresponding to the process flow.

4. A method of manufacturing a memory array, comprising:

selecting a value of a memory cell capacity of a memory die;

determining a cost to fabricate the memory die having the selected memory cell capacity;

selecting a first assembly and packaging method for assembling a plurality of memory die having the selected memory cell capacity into the memory array;

determining a cost to assemble the plurality of memory die into the memory array using the first assembly and packaging method;

determining an overall cost of manufacturing the memory array by combining the costs of fabricating the plurality of memory die and assembling and packaging the die using the first assembly and packaging method;

selecting a second assembly and packaging method for assembling a plurality of memory die having the selected memory cell capacity into the memory array;

determining a cost to assemble the plurality of memory die into the memory array using the second assembly and packaging method; and

determining an overall cost of manufacturing the memory array by combining the costs of fabricating the plurality of memory die and assembling and packaging the die using the second assembly and packaging method.

5. The method of claim 4, further comprising the step of:

manufacturing the memory array using the assembly and packaging method which results in a lower overall manufacturing cost.

6. The method of claim 4, wherein the step of determining a cost to fabricate the memory die further comprises:

selecting a fabrication process flow for fabricating the memory die; and

selecting a yield function corresponding to the process flow.

7. A method of manufacturing a memory array, comprising:

selecting a first value of a memory cell capacity of a memory die;

determining a cost to fabricate the memory die having a memory cell capacity equal to the first value;

selecting an assembly and packaging method for assembling a plurality of memory die having the first memory cell capacity value into the memory array;

determining a cost to assemble the plurality of memory die having the first memory cell capacity value into the memory array using the selected assembly and packaging method;

determining an overall cost of manufacturing the memory array by combining the costs of fabricating the plurality of memory die and of assembling and packaging the die;

selecting a second value of a memory cell capacity of a memory die;

determining a cost to fabricate the memory die having a memory cell capacity equal to the second value;

selecting an assembly and packaging method for assembling a plurality of memory die having the second memory cell capacity value into the memory array;

determining a cost to assemble the plurality of memory die having the second memory cell capacity value into the memory array using the selected assembly and packaging method; and

determining an overall cost of manufacturing the memory array by combining the costs of fabricating the plurality of memory die and of assembling and packaging the die.

8. The method of claim 7, further comprising the step of:

manufacturing the memory array using the memory die capacity value and assembly and packaging method which results in the lower overall manufacturing cost.

9. The method of claim 7, wherein the step of determining a cost to fabricate the memory die further comprises:

selecting a fabrication process flow for fabricating the memory die; and

selecting a yield function corresponding to the process flow.