System for transferring data having a generator for generating a plurality of transfer extend entries in response to a plurality of commands received

• US 6,324,594 B1
• Filed: 12/31/1998
• Issued: 11/27/2001
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Noeldner, David R., Ellis, Jackson L., Springberg, David M., Weston-Lewis, Graeme M.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): DU, THUAN N
• Application Number:
  US09/223,878
• Time in Patent Office: 1,062 Days
• Field of Search: 710/5, 710/22-24, 710/35, 709/101, 711/1, 711/100, 711/133, 711/159
• US Class Current: 710/5
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands. Automatic TE entry generation and storage to buffer memory, and automatic TE retrieval from the buffer memory and execution of entire command threads are further features provided by the present invention. As a result, bus command response latency is decreased by reducing the delay for the command to be started and at the end of the data transfer for status to be send. Disk efficiency is increased by reducing the latency to back-fill or empty a buffer memory segment of data that will be transferred. Furthermore, the present invention is a low-cost trade-off between hardware and firmware functionality.

Claims

1. A method of data transfer between a peripheral device and a host computer, the method comprising the steps of:

(A) generating a plurality of transfer extend entries in the peripheral device in response to a plurality of commands received from the host computer;

(B) arranging the plurality of transfer extend entries into at least one thread in response to step (A);

(C) interrupting a processor of the peripheral device in response to starting a new thread of the at least one thread; and

(D) interrupting the processor in response to completing the new thread.

2. The method of claim 1 wherein the transfer extend entry includes a length of a desired transfer.

3. The method of claim 2 wherein the transfer extend entry includes a next pointer.

4. The method of claim 3 wherein the transfer extend entry includes at least one of the control bits Stop, Stat, DRel, SRel and Data.

5. The method of claim 4 wherein the transfer extend includes a QTag and a QCode.

6. The method of claim 1 wherein the generating step generates a transfer extend entry for a respective command.

7. The method of claim 1 wherein the transfer extend entry includes a type of selection.

8. The method of claim 1 wherein free pointers are used to generate the transfer extend entry.

9. The method of claim 1 further comprising the step of storing the at least one transfer extend.

10. A data controller of a peripheral device in communication with a host computer, the data controller comprising:

a processor; and

a transfer extend generator configured to (i) generate a plurality of transfer extend entries in response to a plurality of commands received from the host computer, (ii) arrange the plurality of transfer extend entries into at least one thread, (iii) interrupt the processor in response to starting a new thread of the at least one thread, and (iv) interrupt the processor in response to completing the new thread.

11. The data controller of claim 10 wherein the transfer extend generator utilizes free pointers to generate the transfer extend entries.

12. The data controller of claim 10 wherein a transfer extend entry is generated for each read and write command.

13. The data controller of claim 10 wherein the transfer extend generator determines if a command is sequential to a previous command.

14. The data controller of claim 13 wherein the transfer extend generator stores a range value that is used to determine if the command is sequential to a previous command.

15. The data controller of claim 13 wherein the transfer extend generator generates a new transfer extend entry and updates an address value if the command is sequential to a previous command.

16. The data controller of claim 13 wherein the transfer extend generator generates a new transfer extend entry with a Stop bit set and updates an address value if the command is not sequential to a previous command.

17. A peripheral device to a host computer, the peripheral device comprising:

means for generating a plurality of transfer extend entries in response to a plurality of commands received from the host computer;

means for arranging the plurality of transfer extend entries into at least one thread in response to generating;

means for interrupting a processor of the peripheral device in response to starting a new thread of the at least one thread; and

means interrupting the processor in response to completing the new thread.