Physical layer interface and method for arbitration over serial bus using digital line state signals

• US 6,324,611 B1
• Filed: 09/17/1998
• Issued: 11/27/2001
• Est. Priority Date: 09/17/1997
• Status: Expired due to Fees

• Current Assignee: NEC Corporation, Sycord Limited Partnership
• Original Assignee: NEC Corporation
• Inventors: Nyu, Takayuki
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Jean, Frantz B.
• Application Number:
  US09/154,980
• Time in Patent Office: 1,167 Days
• Field of Search: 710/129, 710/71, 710/70, 375/347, 709/250, 709/236, 709/213, 712/1, 712/6, 712/36, 712/301, 370/463
• US Class Current: 710/305
• CPC Class Codes: H04L 12/40084 Bus arbitration

Abstract

A physical layer interface for a serial bus includes a controller for producing parallel data representing a near-end line state of the serial bus. A line transmitter is connected to the controller for converting the parallel data therefrom into serial data and transmitting the serial data to the serial bus. A line receiver is connected to the serial bus for receiving therefrom serial dtaa and converting the received serial data into parallel data representing a far-end line state of the serial bus. A differential line state of the serial bus is detected from the parallel data of the controller and the parallel data of the line receiver. The detected differential line state is the input to the controller. In a modified embodiment, a far-end line state of the serial bus is detected from the near-end line state of the serial bus and a far-end differential signal received by the line receiver and directly supplied to the controller. A differential line state of the serial bus is then detected using the near-end line state and the detected far-end line state and serial data representing the detected diffrential line state is sent through the line transmitter.

Claims

1. A physical layer interface for a serial bus comprising:

a controller for producing parallel data representing a near-end line state of the serial bus;

a line transmitter connected to the controller for converting the parallel data therefrom into serial data and transmitting the serial data to said serial bus;

a line receiver connected to the serial bus for receiving therefrom serial data and converting the received serial data into parallel data representing a far-end line state of the serial bus; and

differential line state detection circuitry for detecting a differential line state of said serial bus from the parallel data of the controller and the parallel data of the line receiver and applying the detected differential line state to said controller.

2. The physical layer interface of claim 1, wherein said serial bus comprises an optical transmission medium.

3. The physical layer interface of claim 1, wherein said line transmitter comprises:

an encoder for converting the parallel data of the controller into a parallel codeword; and

a parallel-to-serial converter for converting the parallel codeword into serial form for transmission, and

wherein said line receiver comprises;

a serial-to-parallel converter for receiving a serial codeword from the serial bus and converting the received codeword into a parallel codeword; and

a decoder for decoding the parallel codeword into parallel data for application to said differential line state detection circuitry.

4. The physical layer interface of claim 1, wherein said differential line state detection circuitry includes a map for mapping the parallel data representing the near-end line state and the parallel data representing the far-end line state to the parallel data representing the differential line state of said serial bus.

5. The physical layer interface of claim 1, wherein said differential line state detection circuitry comprises:

a first circuit responsive to parallel data from the controller for producing a first line state voltage at a common circuit node;

a second circuit responsive to parallel data from the line receiver for producing a second line state voltage at said common circuit node; and

a comparator circuit for comparing a differential line state voltage developed at said common circuit node with a reference potential and producing a signal representative of the differential line state of said serial bus.

6. The physical layer interface of claim 1, wherein said differential line state detection circuitry comprises:

a first differential line state detector including;

a first circuit responsive to lower significant bits of the parallel data of the controller for producing a first line state voltage at a first common circuit node;

a second circuit responsive to higher significant bits of the parallel data from the line receiver for producing a second line state voltage at the first common circuit node; and

a first comparator circuit for comparing a differential line state voltage developed at said first common circuit node with a reference potential and producing lower significant bits of parallel data representative of the differential line state of the serial bus; and

a second differential line state detector including;

a third circuit responsive to higher significant bits of the parallel data from the controller for producing a third line state voltage at a second common circuir node;

a fourth circuit responsive to lower significant bits of the parallel data from the line receiver for producing a fourth line state voltage at the second common circuit node; and

a second comparator circuit for comparing a differential line state voltage developed at the second common circuit node with a reference potential and producing higher significant bits of the parallel data representative of the differential line state of the serial bus.

7. A physical layer interface for a serial bus comprising:

a controller for producing parallel data representing a near-end line state of the serial bus and receiving parallel data representing a far-end differential line state of the serial bus;

a line receiver connected to the serial bus for receiving therefrom serial data and converting the received serial data to parallel data representing said far end differential line state of the serial bus;

far-end line state detection circuitry for detecting a far-end line state of the serial bus from the parallel data of the controller and the parallel data of the line receiver and producing parallel data representing the detected far-end line state of the serial bus;

differential line state detection circuitry for detecting a near-end differential line state of said serial bus from the parallel data of the controller and the parallel data of the far-end line state detection circuitry and producing parallel data representing the detected near-end differential line state of the serial bus; and

a line transmitter for converting the parallel data of the differential line state detection circuitry into serial data and transmitting the serial data to said serial bus.

8. The physical layer interface of claim 7, wherein said serial bus comprises an optical transmission medium.

9. The physical layer interface of claim 7 wherein said line transmitter comprises:

an encoder for converting the parallel data of the differential line state detection circuitry into a parallel codeword; and

a parallel-to-serial converter for converting the parallel codeword into serial form for transmission, and

wherein said line receiver comprises;

a serial-to-parallel converter for receiving a serial codeword from the serial bus and converting the received codeword into a parallel codeword; and

a decoder for decoding the parallel codeword into parallel data for application to said controller and said far-end line state detection circuitry.

10. The physical layer interface of claim 7, wherein said differential line state detection circuitry includes a map for mapping the parallel data representing the near-end line state and the parallel data representing the far-end line state to the parallel data representing the differential line state of said serial bus.

11. The physical layer interface of claim 7, wherein said differential line state detection circuitry comprises:

a first circuit responsive to parallel data from the controller for producing a first line state voltage at a common circuit node;

a second circuit responsive to parallel data from the far-end line state detector for producing a fourth line state voltage at said common circuit node; and

a comparator circuit for comparing a differential line state voltage developed at said common circuit node with a reference potential and producing parallel data representative of the differential line state of said serial bus.

12. A method of arbitration between nodes over a serial bus, comprising the steps of:

a) producing parallel data representing a near-end line state of the serial bus;

b) converting said parallel data into serial data and transmitting the serial data to said serial bus;

c) receiving serial data from said serial bus and converting the received serial data to parallel data representing a far-end line state of the serial bus;

d) converting the parallel data representing the near-end line state and the parallel data representing the far-end line state to parallel data representing a differential line state of the serial bus; and

e) making a decision on the parallel data representing the differential line state.

13. A method of arbitration between nodes over a serial bus, comprising the steps of:

a) producing parallel data representing a near-end line state of the serial bus;

b) receiving serial data from the serial bus and converting the received serial data to parallel data representing a far-end differential line state of the serial bus;

c) making a decision on the parallel data representing the far-end differential line state,

d) converting the parallel data representing the near-end line state and the parallel data representing the far-end differential line state to parallel data representing a far-end line state of the serial bus;

e) converting the parallel data representing the near-end line state and the parallel data representing the far-end line state to parallel data representing a near-end differential line state of the serial bus; and

f) converting the parallel data representing the near-end differential line state into serial data and transmitting the serial data to said serial bus.

14. A transmit/receive circuit connected to a transmission medium, comprising:

a state machine for shifting a transition state according to a differential state of said transmission medium produced by signals simultaneously transmitted thereto and producing an outgoing signal according to said transition state;

a transmit circuit for forwarding the outgoing signal from the state machine onto said transmission medium;

a receive circuit for receiving an incoming signal from said transmission medium; and

a collision synthesizing circuit for synthesizing a collision state of said outgoing and incoming signals and applying the synthesized collision state to said state machine as said differential state.

15. The transmit/receive circuit of claim 14, wherein said collision synthesizing circuit is arranged to:

convert said parallel outgoing signal and said parallel incoming signal to analog signals,

synthesize said collision signal from the analog signals,

convert the synthesized collision signal to a digital signal; and

apply the digital signal to said state machine as said differential state.

16. The transmit/receive circuit of claim 15, wherein said analog signals are three-state signals.

17. A transmit/receive circuit connected to a transmission medium, comprising:

a state machine for shifting a transition state according to a differential state of said transmission medium produced by signals simultaneously transmitted thereto and producing a parallel outgoing signal according to said transition state;

a transmit circuit for converting the parallel outgoing signal from the state machine to a serial line-coded signal and forwarding the serial line-coded signal onto said transmission medium;

a receive circuit for decoding a serial incoming line-coded signal from said transmission medium to a parallel incoming signal; and

a collision synthesizing circuit for synthesizing a collision signal from said parallel outgoing signal and said parallel incoming signal and applying the synthesized collision signal to said state machine as said differential state.

18. The transmit/receive circuit of claim 17, wherein said collision synthesizing circuit is arranged to:

convert said parallel outgoing signal and said parallel incoming signal to analog signals,

synthesize said collision signal from the analog signals,

convert the synthesized collision signal to a digital signal; and

apply the digital signal to said state machine as said differential state.

19. The transmit/receive circuit of claim 17, wherein said analog signals are three-state signals.

20. A transmit/receive circuit connected to a transmission medium, comprising:

a state machine for shifting a transition state according to a differential state of said transmission medium produced by signals simultaneously transmitted thereto and producing an outgoing signal according to said transition state;

a transmit circuit for forwarding an outgoing collision signal onto said transmission medium;

a receive circuit for receiving an incoming collision signal from said transmission medium and applying the received collision signal to said state machine as said differential state;

an outgoing signal synthesizing circuit for synthesizing, from the incoming collision signal received by the receive circuit and the outgoing signal of said state machine, and outgoing signal of an adjacent transmit/receive circuit connected to said transmission medium; and

a collision synthesizing circuit for synthesizing a collision signal from the outgoing signal of said state machine and said synthesized outgoing signal and applying the synthesized collision signal to said transmit circuit as said outgoing collision signal.

21. The transmit/receive circuit of claim 20, wherein said collision synthesizing circuit is arranged to:

convert the outgoing signal of said state machine and said synthesized outgoing signal to analog signals,

synthesize said collision signal from the analog signals,

convert the synthesized collision signal to a digital signal, and

apply the digital signal to said transmit circuit as said outgoing collision signal.

22. The transmit/receive circuit of claim 21, wherein said analog signals are three-state signals.

23. A transmit/receive circuit connected to a transmission medium, comprising:

a state machine for shifting a transition state according to a differential state of said transmission medium produced by signals simultaneously transmitted thereto and producing a parallel outgoing signal according to said transition state;

a transmit circuit for converting the parallel outgoing signal to a serial line-coded signal and forwarding the serial line-coded signal onto said transmission medium;

a receive circuit for receiving an incoming collision signal from said transmission medium and applying the received collision signal to said state machine as said differential state;

an outgoing signal synthesizing circuit for synthesizing, from the incoming collision signal received by the receive circuit and the outgoing signal of said state machine, an outgoing of an adjacent transmit/receive circuit connected to said transmission medium; and

a collision synthesizing circuit for synthesizing a collision signal from the outgoing signal of said state machine and said synthesized outgoing signal and applying the synthesized collision signal to said transmit circuit as said outgoing collision signal.

24. The transmit/receive circuit of claim 23, wherein said collision synthesizing circuit is arranged to:

convert the outgoing signal of said state machine and said synthesized outgoing signal to analog signals,

synthesize said collision signal from the analog signals,

convert the synthesized collision signal to a digital signal, and

apply the digital signal to said transmit circuit as said outgoing collision signal.

25. The transmit/receive circuit of claim 24, wherein said analog signals are three-state signals.