Read lock miss control and queue management

• US 6,324,624 B1
• Filed: 12/28/1999
• Issued: 11/27/2001
• Est. Priority Date: 12/28/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Wolrich, Gilbert, Cutter, Daniel, Wheeler, William, Adiletta, Matthew J.
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US09/473,798
• Time in Patent Office: 700 Days
• Field of Search: 710/52, 710/54, 710/57, 710/58, 710/60, 710/200, 710/240, 710/244, 711/118, 711/139, 711/145, 711/147, 711/150, 711/151, 711/152, 711/156, 711/163, 711/167, 711/168
• US Class Current: 711/152
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if (1) the read lock memory reference request is requesting access to an unlocked memory location and (2) the read lock miss queue contains at least one read lock memory reference request.

Claims

1. A method of managing memory access to random access memory comprises:

fetching a read lock memory reference request; and

placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.

2. The method of claim 1 in which the random access memory is located in a parallel, hardware-based multithreaded processor.

3. The method of claim 1 in which the random access memory comprises a static random access memory.

4. The method of claim 1 further comprises placing the read lock memory reference at the end of a read lock miss queue if the read lock memory reference request is requesting access to a locked memory location.

5. The method of claim 1 further comprises removing the read lock memory reference requests from the read lock miss queue in the order in which they were placed in the read lock miss queue.

6. The method of claim 1 in which the read lock memory reference request is fetched from a read queue.

7. The method of claim 1 in which the read lock memory reference request is fetched from an order queue.

8. The method of claim 1 in which the read lock miss queue contains a number of entries equal to a number of contexts that may execute the read lock memory reference requests minus one.

9. The method of claim 1 further comprises placing a read lock memory reference request in a queue that contains a read lock memory reference request requesting access to the same memory location.

10. An article comprising a computer-readable medium which stores computer-executable instructions for managing memory access to random access memory, the instructions causing a computer to:

fetch a read lock memory reference request; and

place the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.

11. The article of claim 10 in which the random access memory is located in a parallel, hardware-based multithreaded processor.

12. The article of claim 10 in which the random access memory comprises a static random access memory.

13. The article of claim 10 in which the instructions further cause a computer to place the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to a locked memory location.

14. The article of claim 10 in which the instructions further cause a computer to remove the read lock memory reference requests from the read lock miss queue in the order in which they were placed in the read lock miss queue.

15. The article of claim 10 in which the read lock memory reference request is fetched from a read queue.

16. The article of claim 10 in which the read lock memory reference request is fetched from an order queue.

17. The article of claim 10 in which the read lock miss queue contains a number of entries equal to a number of contexts that may execute the read lock memory reference requests minus one.

18. The article of claim 10 in which the instructions further cause a computer to place a read lock memory reference request in a queue that contains a read lock memory reference request requesting access to the same memory location.

19. A controller for managing access to random access memory comprises:

an address content addressable memory that supports locked locations in memory; and

a read lock miss queue that stores read lock memory reference requests that request access to memory locations unlocked in the address content addressable memory when the read lock miss queue contains at least one entry.

20. The controller of claim 19 in which the random access memory is located in a parallel, hardware-based multithreaded processor.

21. The controller of claim 19 in which the random access memory comprises a static random access memory.

22. The controller of claim 19 in which the read lock memory reference requests are stored at the end of the read lock miss queue if the read lock memory reference request requests access to a locked memory location.

23. The controller of claim 19 in which the read lock memory reference requests are removed from the read lock miss queue in the order in which they were placed in the read lock miss queue.

24. The controller of claim 19 in which the read lock miss queue contains a number of entries equal to a number of contexts that may execute the read lock memory reference requests minus one.