Programming flash in a closed system

• US 6,324,628 B1
• Filed: 08/24/1999
• Issued: 11/27/2001
• Est. Priority Date: 08/24/1999
• Status: Expired due to Fees

• Current Assignee: Trimble Navigation Limited (Trimble Inc.)
• Original Assignee: Trimble Navigation Limited (Trimble Inc.)
• Inventors: Chan, Victor G.
• Primary Examiner(s): Lane, Jack A.
• Application Number:
  US09/379,711
• Time in Patent Office: 826 Days
• Field of Search: 711/163, 711/5
• US Class Current: 711/163
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings

Abstract

A method and a system for reprogramming a closed device are disclosed. In one embodiment, the system contains an external memory coupled to a limited access device. The limited access device includes a processor, an internal memory, a select control circuit, an internal data bus, and an external data bus. The internal memory is not accessible except through predefined input and output ports of the select control circuit, which are accessible external to the closed device. The select control circuit selects the external memory as primary memory in response to assertion of a control signal and selects the internal memory as primary memory in response to deassertion of a control signal. The internal data bus transports data within the limited access device which includes the internal memory and the select control circuit and the external data bus transports data between the select control circuit and the external memory.

Claims

1. A system comprising:

an external memory; and

a closed device, coupled to said external memory, wherein said closed device includes;

a processor coupled to said external memory;

an internal memory coupled to said processor, wherein said internal memory is not accessible except access through predefined input and output ports that are internal to said closed device;

a select control circuit coupled to said processor and configured to select said external memory as primary memory in response to assertion of an external control signal and to select said internal memory as primary memory in response to a deassertion of said external control signal;

an internal data bus, coupled with said select control circuit, said processor, and said internal memory, said internal data bus residing solely within said closed device with no external access; and

an external data bus, coupled with said select control circuit and said external memory, configured to transport data between said select control circuit and said external memory.

2. The system as set forth in claim 1, wherein said select control circuit is further configured to transfer data to and from said internal and external data buses and furthermore a mean of isolation between two said buses.

3. The system as set forth in claim 2, wherein said select control circuit enables said internal memory to be updated when said external memory is selected as primary memory.

4. The system as set forth in claim 1 further including a control device, wherein said control signal represents logic states of a program control signal generated by said control device.

5. The system as set forth in claim 1, wherein said control signal is selectively applied to an input port accessible external to said closed device.

6. The system as set forth in claim 1, wherein said primary memory is configured to store supervisory code.

7. The system as set forth in claim 1, wherein said primary memory is configured to store programming code which when executed by a processor, initializes said closed device.

8. The data processing system of claim 1, wherein said closed device further comprises a random access memory (“

RAM”

) coupled to said processor, said random access memory configured to store data.

9. The system as set forth in claim 1, wherein said internal memory is a flash read only memory (“

ROM”

).

10. The system as set forth in claim 1, wherein said select control circuit is a secured access circuit that is configured to control access to memory devices within the system.

11. The system as set forth in claim 1 further comprising at least another external memory externally coupled to said closed device and configured to store data.

12. A method for accessing a closed system comprising:

receiving a program control signal that originates from outside of said closed system;

selecting a primary memory located outside of said closed system and coupled to said closed system as a program memory in response to assertion of said program control signal;

selecting a primary memory located inside of said closed system as program memory in response to deassertion of said program control signal; and

executing instructions received from said program memory.

13. The method as set forth in claim 12 further comprising updating said memory located inside of said closed system when said memory located outside of said closed system is selected as program memory.

14. The method as set forth in claim 12 further comprising initializing said closed system utilizing code stored in said memory located outside of said closed system.

15. The method as set forth in claim 12 further comprising:

utilizing an external data bus to transport data between said memory located outside of said closed system and said select control circuit; and

utilizing an internal data bus to transport data between said memory located inside of said closed system and a select control circuit.

16. The method of claim 15, wherein when said memory located outside of said closed system is selected as primary memory, the method further comprising:

unlocking said memory located inside of said closed system;

loading instructions from said memory located outside of said closed system to said memory located inside of said closed system; and

locking said memory located inside of said closed system.

17. A system comprising:

an external memory;

a closed device, coupled to said external memory, said device comprising an internal memory and a select control circuit coupled to said external memory and said internal memory, said select control circuit configured to;

receive a program control signal from outside of said closed device,

select said external memory located outside of said closed device as program memory in response to an active state of said program control signal,

select said internal memory located inside of said closed device as program memory in response to an inactive state of said program control signal, and

reprogram said internal memory when said external memory is selected as program memory.

18. The system of claim 17, wherein said system includes:

an external bus coupled to said select control circuit and configured to transport data between said external memory and said select control circuit; and

an internal bus coupled to said select control circuit and configured to transport data between said internal memory and said select control circuit.

19. The system of claim 17, wherein said reprogram said internal memory further comprises:

unlocking said internal memory;

updating said internal memory in response to data stored in said external memory; and

locking said internal memory upon completion of updating.

20. The system of claim 17, wherein said external memory further comprises a first bank and a second bank, wherein said first bank is configured to store program code and said second bank is configured to store data.