Network enhanced bios enabling remote management of a computer without a functioning operating system

• US 6,324,644 B1
• Filed: 01/19/1999
• Issued: 11/27/2001
• Est. Priority Date: 03/20/1997
• Status: Expired due to Term

• Current Assignee: Kinglite Holdings Inc.
• Original Assignee: Phoenix Technologies Limited (Pharaoh Acquisition LLC)
• Inventors: Burton, Michael Peter R., Rakavy, Yuval, Anderson, Ian, Garsten, Andrew, Roche, James
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): Patel, Nitin
• Application Number:
  US09/232,687
• Time in Patent Office: 1,043 Days
• Field of Search: 713/1, 713/2, 713/100, 713/323, 713/330, 710/261, 710/269
• US Class Current: 713/1
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/327 Alarm or error message display
• CPC Class Codes: G06F 9/4416 Network booting; Remote initial program loading [RIPL]

Abstract

A method and system of communicating with a computer through a network prior to booting the computer'"'"'s operating system or after operating system failure is provided. A multitasking kernel is implemented in a network enhanced BIOS. External references in a NIC device driver are resolved to reference services provided by the network enhanced BIOS. A workstation coupled to the computer through a network may be used to access and set status on the computer prior to loading the operating system or after operating system failure. The multitasking kernel may be operated simultaneously with a conventional BIOS. The computer may be further provided with a means for alerting the workstation in the event of a POST failure or operating system crash.

Claims

1. A method of operating a computer, said computer including a central processing unit (CPU), said CPU operating in at least two modes including a real mode and a protected mode, said method comprising:

loading and executing a first basic input/output system (BIOS) on said CPU in real mode, said first BIOS having an initial portion and a subsequent portion, said first BIOS performing a power on system test of said computer;

loading and executing a second BIOS on said CPU in protected mode after execution of said initial portion of said first BIOS; and

executing said second BIOS and said subsequent portion of said first BIOS on said CPU in alternate portions such that said second BIOS and said subsequent portion of said first BIOS appear to execute simultaneously.

2. A method of operating a computer, said computer including a central processing unit (CPU) and a timer for providing a timer interrupt, said CPU operating in at least two modes including a real mode and a protected mode, said method comprising:

loading and executing a first basic input/output system (BIOS) on said CPU in real mode, said first BIOS having an initial portion and a subsequent portion, said first BIOS performing a power on system test of said computer; and

loading and executing a second BIOS on said CPU in protected mode after execution of said initial portion of said first BIOS,

said second BIOS and said subsequent portion of said first BIOS being executed on said CPU in alternate portions such that said second BIOS and said subsequent portion of said first BIOS appear to execute simultaneously by;

(a) vectoring said timer interrupt to a jump program which executes in real mode,

when executed, said jump program saves the current state of the real mode first BIOS and transfers control of the CPU to a portion of code which restores the state of the protected mode second BIOS and switches said CPU to protected mode;

(b) executing a portion of said protected mode second BIOS;

(c) switching said CPU to real mode and saving the current state of the protected mode second BIOS;

(d) restoring said real mode first BIOS to said saved state; and

(e) executing said real mode first BIOS until interrupted by said timer interrupt, said real mode first BIOS will execute until interrupted by said timer interrupt at which point said protected mode second BIOS will be restored to a saved state and given CPU control.

3. An apparatus for operating a computer, comprising:

a first basic input/output system (BIOS) that includes an initial portion and a subsequent portion;

a second BIOS; and

a central processing unit (CPU) coupled to the first BIOS and the second BIOS, and can operate in at least two modes including a real mode and a protected mode, said CPU to load and execute the first BIOS in real mode, said CPU to load and execute the second BIOS in protected mode after execution of the initial portion of the first BIOS, said CPU to execute said second BIOS and said subsequent portion of said first BIOS in alternate portions such that said second BIOS and said subsequent portion of said first BIOS appear to execute simultaneously.

4. The apparatus of claim 3 wherein the first BIOS for performing a power on system test of said computer.

5. The apparatus of claim 3 further comprising a timer to provide a timer interrupt, said CPU, in response to detecting the timer interrupt, to (i) save the current state of the real mode first BIOS, (ii) restore the state of the protected mode second BIOS and switch to protected mode, (iii) execute a portion of said protected mode second BIOS, (iv) switch said CPU to real mode and save the current state of the protected mode second BIOS, (v) restore said real mode first BIOS to said saved state, and (vi) execute said real mode first BIOS.