Memory test device and method capable of achieving fast memory test without increasing chip pin number

• US 6,324,666 B1
• Filed: 12/24/1998
• Issued: 11/27/2001
• Est. Priority Date: 04/20/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakamoto, Yukio
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Lamarre, Guy J.
• Application Number:
  US09/220,366
• Time in Patent Office: 1,069 Days
• Field of Search: 714/718, 714/25, 714/719, 714/42, 714/710, 714/723, 714/734, 714/735, 714/736, 714/738, 714/739, 714/732, 714/35, 714/45, 714/711, 365/200-201, 365/189.02, 365/194, 711/220, 707/100-101
• US Class Current: 714/736
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A memory test device that issues a test pattern read request to a memory, captures test pattern signals placed by the memory on a data input/output bus in response to the test pattern read request, and compares the test pattern signals with their expected values. This can solve a problem involved in a conventional memory test device in that because the pin width of data pins is narrower than the bus width of the data input/output bus that connects a memory and a data bus controller, even if the memory reads test pattern signals in accordance with the width of the data input/output bus, the test pattern signals cannot be sent to the tester without being divided, and hence the tester cannot achieve the quick test of the memory.

Claims

1. A memory test device comprising:

issue means for issuing test pattern associated data for designating a test pattern;

expected value generating means for generating expected values of said test pattern designated by said test pattern associated data;

memory control means for issuing a test pattern read request to a memory in response to the test pattern associated data; and

comparing means for comparing said expected values with said test pattern which is read from said memory in response to the test pattern read request, and obtained by said comparing means through a data input/output bus.

2. The memory test device as claimed in claim 1, wherein said issue means comprises pattern number issue means for issuing a test pattern number as the test pattern associated data.

3. The memory test device as claimed in claim 2, further comprising test pattern generating means for generating said test pattern designated by said test pattern number, and for supplying the data input/output bus with said test pattern generated by said test pattern generating means, wherein said memory control means issues a test pattern write request to said memory in response to said test pattern number issued by said test number issue means.

4. The memory test device as claimed in claim 2, wherein said pattern number issue means comprises a pattern number issue procedure memory, and issues said test pattern number using said pattern number issue procedure memory.

5. The memory test device as claimed in claim 1, wherein said issue means comprises program issue means for issuing a data pattern as the test pattern associated data.

6. The memory test device as claimed in claim 5, further comprising test pattern generating means for generating said test pattern in accordance with the data pattern output from said program issue means, and for supplying the data input/output bus with said test pattern generated by said test pattern generating means, wherein said memory control means issues a test pattern write request to said memory in response to the data pattern issued by said program issue means.

7. The memory test device as claimed in claim 1, further comprising bus disconnection means for disconnecting said data input/output bus from an internal data bus, when said memory control means issues to said memory one of a read request and write request of said test pattern.

8. The memory test device as claimed in claim 1, further comprising total decision means for producing a decision result that a defective bit is absent in said memory if comparing means outputs a positive result that said test pattern exactly agrees with said expected values, and for producing a decision result that a defective is present in said memory if said comparing means outputs a negative result that said test pattern disagrees with at least one of said expected values.

9. The memory test device as claimed in claim 1, further comprising setting means for setting a test mode of said memory to carry out writing of said memory through said data input/output bus.

10. The memory test device as claimed in claim 1, further comprising identification means for identifying a defective bit in said memory from compared results output from said comparing means.

11. The memory test device as claimed in claim 1, wherein said identification means obtains an LT (laser trimming) remedial address from the defective bit of said memory.

12. The memory test device as claimed in claim 1, further comprising modification means for altering at least part of data pattern in said issue means and in said test pattern generating means.

13. A memory test method comprising the steps of:

issuing test pattern associated data for designating a test pattern;

generating expected values of said test pattern designated by said test pattern associated data;

issuing a test pattern read request to a memory in response to the test pattern associated data; and

comparing said expected values with said test pattern which is read from said memory in response to the test pattern read request, and obtained through a data input/output bus.

14. The memory test method as claimed in claim 13, wherein the step of issuing test pattern associated data issues a test pattern number as the test pattern associated data.

15. The memory test method as claimed in claim 14, further comprising the steps of:

generating said test pattern designated by said test pattern number, and supplying the data input/output bus with said test pattern; and

issuing a test pattern write request to said memory in response to said test pattern number.

16. The memory test method as claimed in claim 13, wherein the step of issuing test pattern associated data issues a data pattern as the test pattern associated data.

17. The memory test method as claimed in claim 16, further comprising the steps of:

generating said test pattern in accordance with the data pattern, and supplying the data input/output bus with said test pattern; and

issuing a test pattern write request to said memory in response to the data pattern.

18. The memory test method as claimed in claim 13, further comprising the step of disconnecting said data input/output bus from an internal data bus, when one of a read request and write request of said test pattern is issued to said memory.

19. The memory test method as claimed in claim 13, further comprising the step of identifying a defective bit of said memory from compared results of said test pattern with said expected values.

20. The memory test method as claimed in claim 19, further comprising the step of obtaining an LT (laser trimming) remedial address from the defective bit of said memory.