High speed CMOS imager with motion artifact supression and anti-blooming
First Claim
1. A method of operating a photosensitive pixel, the method comprising:
- biasing first and second transfer gates disposed in a vicinity of a photoactive region of a semiconductor substrate to accumulate photocharges in the photoactive region during a pixel integration period;
raising a bias voltage on the first transfer gate and lowering a bias voltage on the second transfer gate to transfer the accumulated photocharges to a sense node via a region of the semiconductor substrate disposed below the first transfer gate; and
subsequently biasing the first and second transfer gates to transfer additional photocharges in the photoactive region to a power supply node via a region of the semiconductor substrate disposed below the second transfer gate without passing the additional photocharges through the sense node.
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Abstract
An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node. The image sensor includes a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node. The imager can operate at high shutter speeds with simultaneous integration of pixels in the array. High quality images can be produced free from motion artifacts. High quantum efficiency, good blooming control, low dark current, low noise and low image lag can be obtained.
90 Citations
11 Claims
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1. A method of operating a photosensitive pixel, the method comprising:
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biasing first and second transfer gates disposed in a vicinity of a photoactive region of a semiconductor substrate to accumulate photocharges in the photoactive region during a pixel integration period;
raising a bias voltage on the first transfer gate and lowering a bias voltage on the second transfer gate to transfer the accumulated photocharges to a sense node via a region of the semiconductor substrate disposed below the first transfer gate; and
subsequently biasing the first and second transfer gates to transfer additional photocharges in the photoactive region to a power supply node via a region of the semiconductor substrate disposed below the second transfer gate without passing the additional photocharges through the sense node. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operating an image sensor having an array of photosensitive pixels, the method comprising:
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accumulating photocharges in a respective photoactive region of a semiconductor substrate in each pixel of the array during a common pixel integration period;
raising a bias voltage on a respective first transfer gate and lowering a bias voltage on a respective second transfer gate disposed in a vicinity of each photoactive region to transfer the accumulated photocharges from each photoactive region to a respective sense node; and
subsequently biasing the respective first and second transfer gates to transfer additional photocharges in the photoactive regions to respective power supply nodes via respective regions of the semiconductor substrate below the second transfer gates, without passing the additional photocharges through the respective sense nodes. - View Dependent Claims (9, 10, 11)
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Specification