CMOS compatible SOI process

• US 6,326,288 B1
• Filed: 07/06/2000
• Issued: 12/04/2001
• Est. Priority Date: 07/06/1999
• Status: Expired due to Term

• Current Assignee: Elmos Semiconductor SE
• Original Assignee: Elmos Semiconductor AG
• Inventors: Bornefeld, Ralf
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): MENZ, LAURA MARY
• Application Number:
  US09/610,886
• Time in Patent Office: 516 Days
• Field of Search: 438/585, 438/658, 438/660, 438/194, 438/283, 438/291, 438/195, 438/589, 438/270, 438/259, 438/422, 438/404, 438/408, 438/409, 438/338, 257/355, 257/348, 257/356, 257/335
• US Class Current: 438/585
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

In a method for producing an integrated circuit using a CMOS process, in particular a HV CMOS process, components are formed within troughs of different depths and of a first conductivity type, in particular N-type troughs, which are formed in a substrate layer of a second conductivity type opposite to the first conductivity type, in particular a P-type substrate. Further, a SOI wafer substrate is used that comprises a top substrate layer for forming the CMOS components, a lateral insulation layer provided beneath the substrate layer, and a support layer arranged beneath the insulation layer. The top substrate layer has a thickness less than or equal to the greatest trough depth of the CMOS process. The top substrate layer is provided with trench insulation areas down to the subjacent lateral insulation layer, and components are formed within the areas of the silicon layer intermediate the trench insulation areas using the CMOS process, wherein the troughs of the greatest depth (high-voltage N-type trough) extend to the insulation layer and fill the respective area entirely, and wherein components are integrated directly in the troughs of the greatest depth (high-voltage N-type trough), whereas, for components requiring a lesser trough depth, the troughs (logic N-type trough) surrounding these components are provided in troughs of the greatest depth (high-voltage N-type trough).

Claims

1. A method for producing an integrated circuit using a CMOS process, in particular a high voltage CMOS process, wherein components are formed within troughs of different depths and of a first conductivity type, in particular N-type troughs, which are formed in a substrate layer of a second conductivity type opposite to the first conductivity type, in particular a P-type substrate, the method being characterized in that

an SOI wafer substrate (10) is used that comprises a top substrate layer (26) for forming the CMOS components (34-40), a lateral insulation layer (24) provided beneath the substrate layer, and a support layer (22) arranged beneath the insulation layer,

the top substrate layer (26) has a thickness less than or equal to the greatest trough depth of the CMOS process,

the top substrate layer (26) is provided with vertical insulation areas (28) down to the subjacent lateral insulation layer (24), and

components (34-40) are formed within areas (32) of the substrate layer (26) intermediate the vertical insulation areas (28) using the CMOS process, wherein the troughs (42, 44) of the greatest depth (high-voltage N-type trough) extend to the insulation layer (24) and fill the respective area (32) entirely, and wherein components (34, 36) are integrated directly in the troughs (42, 44) of the greatest depth (high-voltage N-type trough), whereas, for components (38, 40) requiring a lesser trough depth, the troughs (46, 48) (logic N-type trough) surrounding these components are provided in troughs (42, 44) of the greatest depth (high-voltage N-type trough).

2. The method of claim 1, wherein the vertical insulation areas (28) are formed by vertically etching a trench into the substrate layer (26) down to the lateral insulation layer (24) and by successively providing or forming an insulating material in the trench.

3. An integrated circuit comprising CMOS components (34-40) produced in accordance with claim 1.