Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors

• US 6,326,642 B1
• Filed: 08/17/1999
• Issued: 12/04/2001
• Est. Priority Date: 05/29/1992
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/375,352
• Time in Patent Office: 840 Days
• Field of Search: 257/59, 257/72, 257/344-355
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Claims

1. A semiconductor device comprising:

at least two p-channel thin film transistors, each of the p-channel thin film transistors including;

a semiconductor island over a substrate;

a source region, a drain region and a channel region formed between the source and drain regions;

a gate electrode adjacent to the channel region with a gate insulating film therebetween,

wherein the two p-channel thin film transistors are connected in series to form a dual gate structure.

2. A device according to claim 1, wherein an off current from each of the p-channel thin film transistors is less than 10⁻

12 A where a voltage of the drain region is 1V.

3. A device according to claim 1 further comprising an interlayer insulating film including boro-phosphosilicate glass.

4. A device according to claim 1, wherein each of the source and drain regions comprises boron.

5. A device according to claim 1 further comprising a blocking film between the substrate and the semiconductor island,

wherein the substrate is a glass substrate;

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

6. A display device comprising:

a pixel portion and a driving circuit portion;

at least two p-channel thin film transistors being formed in the pixel portion, each of the p-channel thin film transistors including;

a semiconductor island over a substrate;

a source region, a drain region and a channel region formed between the source and drain regions;

a gate electrode adjacent to the channel region with a gate insulating film therebetween,

wherein the two p-channel thin film transistors are connected in series to form a dual gate structure.

7. A device according to claim 6 further comprising a blocking film between the substrate and the semiconductor island,

wherein the substrate is a glass substrate;

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

8. A device according to claim 6, wherein an off current from each of the p-channel thin film transistors is less than 10⁻

12 A where a voltage of the drain region is 1V.

9. A device according to claim 6 further comprising an interlayer insulating film including boro-phosphosilicate glass.

10. A device according to claim 6, wherein each of the source and drain regions comprises boron.

11. A semiconductor device comprising a transmission gate including a CMOS circuit, said CMOS circuit including at least an n-channel thin film transistor and a p-channel thin film transistor, each of the n-channel and p-channel thin film transistors including:

a semiconductor island over a glass substrate;

a source region, a drain region and a channel region formed between the source and drain regions;

a gate electrode adjacent to the channel region with a gate insulating film therebetween;

blocking film between the glass substrate and the semiconductor island, said blocking film including,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

12. A device according to claim 11,

wherein an off current from the p-channel thin film transistors is less than 10^{− 12} A where a voltage of the drain region is 1V.

13. A device according to claim 11 further comprising an interlayer insulating film including boro-phosphosilicate glass.

14. A device according to claim 11, wherein each of the source and drain regions of the p-channel thin film transistor comprises boron.

20. A device according to claim 11, wherein each of the source and drain regions of the n-channel thin film transistor comprises phosphorus.

15. A display device comprising:

a pixel portion and a driving circuit portion;

a transmission gate being formed in the driving circuit portion and including a CMOS circuit, said CMOS circuit including at least an n-channel thin film transistor and a p-channel thin film transistor, each of the n-channel and p-channel thin film transistors including;

a semiconductor island over a glass substrate;

a source region, a drain region and a channel region formed between the source and drain regions;

a gate electrode adjacent to the channel region with a gate insulating film therebetween;

a blocking film between the glass substrate and the semiconductor island, said blocking film including,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

16. A device according to claim 15, wherein an off current from the p-channel thin film transistor is less than 10⁻

12 A where a voltage of the drain region is 1V.

17. A device according to claim 15 further comprising an interlayer insulating film including boro-phosphosilicate glass.

18. A device according to claim 15, wherein each of the source and drain regions of the p-channel thin film transistor comprises boron.

19. A device according to claim 15, wherein each of the source and drain regions of the n-channel thin film transistor comprises phosphorus.

21. A semiconductor device comprising:

at least a first p-channel thin film transistor and a second p-channel thin film transistor, each of the first and second p-channel thin film transistors including;

a first semiconductor island over a substrate;

a first source region, a first drain region and a first channel region formed between the first source and drain regions;

a first gate electrode adjacent to the first channel region with a first gate insulating film therebetween;

wherein the first and second p-channel thin film transistors are connected in series to form a dual gate structure;

a transmission gate including a CMOS circuit,

said CMOS circuit including at least an n-channel thin film transistor and a third p-channel thin film transistor, each of the n-channel and the third p-channel thin film transistors including;

a second semiconductor island over the substrate;

a second source region, a second drain region and a second channel region formed between the second source and drain regions;

a second gate electrode adjacent to the second channel region with a second gate insulating film therebetween.

22. A device according to claim 21,

wherein an off current from each of the first, second and third p-channel thin film transistors is less than 10− 12 A where a voltage of the drain region is 1V.

23. A device according to claim 21 further comprising an interlayer insulating film including boro-phosphosilicate glass.

24. A device according to claim 21,

wherein each of the first source and drain regions of each of the first and second p-channel thin film transistors and each of the second source and drain regions of the third p-channel thin film transistor comprise boron.

25. A device according to claim 21,

wherein each of the second source and drain regions of the n-channel thin film transistor comprises phosphorus.

26. A device according to claim 21 further comprising:

a blocking film between the substrate and each of the first and second semiconductor islands,

wherein the substrate is a glass substrate,

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.