FPGA-based communications access point and system for reconfiguration

• US 6,326,806 B1
• Filed: 03/29/2000
• Issued: 12/04/2001
• Est. Priority Date: 03/29/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Smith, Michael J. S., Fallside, Hamish T.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/539,163
• Time in Patent Office: 615 Days
• Field of Search: 326/47, 326/38, 326/41, 326/40, 326/46
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

An FPGA-based communications access point and system for reconfiguration of the FPGA via a communications channel are described in various embodiments. One embodiment includes a physical interface circuit, a storage element (e.g., a RAM), an FPGA, and a configuration control circuit. The physical interface circuit is arranged for connection to a communications channel and is coupled to the FPGA. The configuration control circuit includes a controlling circuit (e.g., a PLD) and a memory circuit (e.g., a PROM). The PROM is configured with an initial configuration bitstream for the FPGA. The initial configuration bitstream implements both a communications protocol and a control function that writes configuration bits received by the FPGA via the communications channel to the RAM. The control function also generates a reconfiguration signal responsive to a first predetermined condition. The PLD is configured to load the initial configuration bitstream from the PROM into the FPGA, and, responsive to the reconfiguration signal from the FPGA, to load a second configuration bitstream from the RAM into the FPGA. The control function may be configured to interact with standard network programs such as FTP (file transfer protocol) or custom programs.

Claims

1. A circuit arrangement for reconfiguration of an FPGA over a communications channel, comprising:

a physical interface circuit arranged for connection to a communications channel;

a storage element;

an FPGA coupled to the storage element and to the physical interface circuit;

a configuration control circuit coupled to the FPGA and to the storage element, the configuration control circuit being configured and arranged to load the FPGA with an initial configuration bitstream that implements both a communications protocol and a control function, wherein the control function writes configuration bits received by the FPGA from the physical interface circuit to the storage element and generates a reconfiguration signal responsive to a first predetermined condition, the configuration control circuit being further configured and arranged to load a second configuration bitstream from the storage element into the FPGA responsive to the reconfiguration signal from the FPGA.

2. The circuit arrangement of claim 1, wherein the configuration control circuit comprises:

a memory device for storing the initial configuration bitstream; and

a controlling circuit configured and arranged to load the FPGA with the initial configuration bitstream from the memory device and to load the second configuration bitstream from the storage element into the FPGA.

3. The circuit arrangement of claim 2, wherein the memory device is a PROM.

4. The circuit arrangement of claim 2, wherein the controlling circuit is implemented in a programmable logic device (PLD).

5. The circuit arrangement of claim 1, wherein the storage element is a RAM.

6. The circuit arrangement of claim 1, wherein the communications protocol is a TCP/IP stack.

7. The circuit arrangement of claim 6, wherein the physical interface circuit includes an Ethernet transceiver.

8. The circuit arrangement of claim 6, wherein the physical interface circuit includes a wireless transceiver.

9. The circuit arrangement of claim 1, wherein the configuration control circuit is further configured to set up the FPGA for partial configuration and to load a partial configuration bitstream from the storage element to the FPGA responsive to a partial-reconfigure signal from the FPGA.

10. The circuit arrangement of claim 1, wherein the configuration control circuit is further configured and arranged to read back configuration data from the FPGA to the storage element responsive to a read-back signal from the FPGA.

11. The circuit arrangement of claim 1, wherein:

the storage element is implemented in the FPGA by the initial configuration bitstream, and

the second configuration bitstream is a partial reconfiguration bitstream, and the storage element is not reconfigurable by the partial reconfiguration bitstream.

12. An FPGA-based communications access point, comprising:

a physical interface circuit arranged for connection to a communications channel;

a memory device comprising an initial configuration bitstream for implementing a communications protocol on an FPGA and further implementing one or more application-specific functions to be performed by the FPGA over the communications channel;

an FPGA coupled to the memory device and to the physical interface circuit, the FPGA having a configuration interface; and

a controlling circuit coupled to the memory device and to the configuration interface of the FPGA, the controlling circuit being configured to load the initial configuration bitstream from the memory device into the FPGA upon occurrence of a predetermined event.

13. The communications access point of claim 12, wherein the memory device is a PROM.

14. The communications access point of claim 12, wherein the controlling circuit is implemented in a programmable logic device (PLD).

15. The communications access point of claim 12, wherein the communications protocol is a TCP/IP stack.

16. The communications access point of claim 15, wherein the physical interface circuit includes an Ethernet transceiver.

17. The communications access point of claim 15, wherein the physical interface circuit includes a wireless transceiver.

18. A circuit arrangement for reconfiguration of an FPGA via a communications channel, comprising:

a physical interface circuit arranged for connection to a communications channel;

a storage element;

a memory device configured with an initial configuration bitstream for implementing a communications protocol on the FPGA and further for implementing a control function that writes configuration bits received by the FPGA from the physical interface circuit to the storage element and generates a reconfiguration signal responsive to a first predetermined condition;

an FPGA coupled to the storage element, the memory device, and the physical interface circuit, the FPGA having a configuration interface; and

a controlling circuit coupled to the storage element, the memory device, and the configuration interface of the FPGA, the controlling circuit being configured to load the initial configuration bitstream from the memory device into the FPGA responsive to a second predetermined condition, and to load a second configuration bitstream from the storage element into the FPGA responsive to the reconfiguration signal from the FPGA.

19. The circuit arrangement of claim 18, wherein the memory device is a PROM.

20. The circuit arrangement of claim 18, wherein the controlling circuit is implemented in a programmable logic device (PLD).

21. The circuit arrangement of claim 18, wherein the storage element is a RAM.

22. The circuit arrangement of claim 18, wherein the controlling circuit is further configured to load the initial configuration bitstream from the memory device to the FPGA responsive to a cold-configure signal from the FPGA.

23. The circuit arrangement of claim 18, wherein the controlling circuit is further configured to load a third configuration bitstream from the memory device to the FPGA.

24. The circuit arrangement of claim 18, wherein the controlling circuit is further configured to set up the FPGA for partial configuration and to load a partial configuration bitstream from the storage element to the FPGA.

25. The circuit arrangement of claim 24, wherein a partial configuration of the FPGA is initiated responsive to a partial-reconfigure signal from the FPGA.

26. The circuit arrangement of claim 18, wherein the controlling circuit is further configured and arranged to transfer the initial configuration bitstream from the memory device to the storage element.

27. The circuit arrangement of claim 26, wherein the initial configuration bitstream is transferred from the memory device to the storage element responsive to a dump-memory signal from the FPGA.

28. The circuit arrangement of claim 18, wherein the controlling circuit is further configured and arranged to read back configuration data from the FPGA and write the configuration data to the storage element.

29. The circuit arrangement of claim 28, wherein the read back of the configuration data is performed responsive to a read-back signal from the FPGA.

30. The circuit arrangement of claim 18, wherein the wherein the controlling circuit is further configured to:

load an initial configuration bitstream from the memory device to the FPGA responsive to a cold-configure signal from the FPGA;

set up the FPGA for partial configuration and load a partial configuration bitstream from the storage element to the FPGA responsive to a partial-reconfigure signal from the FPGA;

transfer the initial configuration bitstream from the memory device to the storage element responsive to a dump-memory signal from the FPGA; and

read back configuration data from the FPGA and write the configuration data to the storage element responsive to a read-back signal from the FPGA.

31. The circuit arrangement of claim 18, wherein:

the storage element is implemented in the FPGA by the initial configuration bitstream, and

the second configuration bitstream is a partial reconfiguration bitstream, and the storage element is not reconfigurable by the partial reconfiguration bitstream.

32. A method for reconfiguration of an FPGA via a communications channel, comprising:

configuring the FPGA with an initial configuration bitstream that implements both a communications protocol and a control function;

receiving a second configuration bitstream from the communications channel at the FPGA via the implemented communications protocol;

storing the second configuration bitstream in a storage element under control of the implemented control function; and

reconfiguring the FPGA with the second configuration bitstream from the storage element.

33. The method of claim 32, further comprising initiating reconfiguration with the second configuration bitstream in response to a signal from the FPGA.

34. The method of claim 32, wherein:

configuring the FPGA takes place under control of a bootstrapping circuit; and

reconfiguring the FPGA takes place under control of a reconfiguration control circuit implemented in the FPGA as a result of configuring the FPGA.

35. The method of claim 32, wherein configuring the FPGA with the initial configuration bitstream comprises loading the initial configuration bitstream from a PROM to the FPGA.

36. The method of claim 32, wherein the storage element is a RAM.

37. The method of claim 32, wherein the FPGA is configured and reconfigured under control of a configuration control circuit.

38. The method of claim 37, wherein the configuration control circuit is implemented with a programmable logic device (PLD).

39. The method of claim 37, further comprising:

providing a configuration instruction signal from the configuration control circuit to the FPGA; and

reconfiguring the FPGA in one of a plurality of operating modes specified by the configuration instruction signal, wherein the plurality of operating modes includes;

a first mode of reconfiguring the FPGA with the initial configuration bitstream,

a second mode of reconfiguring the FPGA with a full configuration bitstream from the storage element, and

a third mode of partially reconfiguring the FPGA with a partial configuration bitstream from the storage element.

40. The method of claim 32, wherein:

the storage element is implemented in the FPGA by the initial configuration bitstream, and

reconfiguring the FPGA performs a partial reconfiguration, the storage element not being reconfigured by the partial reconfiguration.