Apparatus for translating a voltage

• US 6,326,839 B2
• Filed: 12/07/2000
• Issued: 12/04/2001
• Est. Priority Date: 07/29/1996
• Status: Expired due to Term

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Townsend and Townsend and Crew LLP (Kilpatrick Townsend & Stockton LLP)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US09/732,793
• Publication Number:
  US 20010001230A1
• Time in Patent Office: 362 Days
• Field of Search: 327/536, 327/589, 327/537, 327/543, 327/538, 327/333
• US Class Current: 327/589
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/071 adapted to generate a negative voltage output from a positive voltage source
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator. When the substrate voltage is above the desired level, the comparator generates a pump activating signals to a pump signal generator which, in turn, generates the necessary signal to cause the charge pump to operate.

Claims

1. An apparatus for translating voltages comprising:

control signal means for generating first and second mutually exclusive low voltage control signals;

a first capacitance having a first terminal coupled for receiving the first control signal;

a second capacitance having a first terminal coupled for receiving the second control signal;

a first transistor having a first current flowing terminal coupled to a high voltage current source, a second current flowing terminal coupled to a second terminal of the first capacitance, and a control terminal coupled to a second terminal of the second capacitance;

a second transistor;

having a first current flowing terminal coupled to the high voltage current source, a second current flowing terminal coupled to the second terminal of the second capacitance, and a control terminal coupled to the second terminal of the first capacitance;

wherein the second transistor conducts current when the first control signal is received by the first capacitance; and

wherein the first transistor conducts current when the second control signal is received by the second capacitance,

a third transistor having a first current flowing terminal coupled to the high voltage current source, a control terminal coupled to the second terminal of the first capacitance, and a second current flowing terminal;

a fourth transistor having a first current flowing terminal coupled to the second current flowing terminal of the third transistor, a second current flowing terminal coupled to a ground potential, and a control terminal coupled to the first terminal of the first capacitance;

wherein one of the third or fourth transistor conducts when the first signal is received by the first capacitance; and

wherein the other of the third or fourth transistor conducts when the second signal is received by the second capacitance.

2. The apparatus according to claim 1 wherein the first control signal comprises a low portion and a high portion, wherein the second control signal comprises a low portion and a high portion, and wherein the low portion of the first control signal is mutually exclusive with the low portion of the second control signal.

3. The apparatus according to claim 2 wherein the low portion of the first and second control signals are each approximately zero volts, and wherein the high portion of the first and second control signals are each approximately 1.5 volts.

4. The apparatus according to claim 3 wherein the first and second transistors each comprise PMOS transistors.

5. The apparatus according to claim 4 wherein the third transistor comprises a PMOS transistor and the fourth transistor comprises a NMOS transistor.

6. The apparatus according to claim 5 wherein the high voltage current source is approximately five volts.

7. An apparatus for translating a substrate voltage comprising:

control signal means for generating first and second mutually exclusive low voltage control signals;

a first capacitance having a first terminal coupled for receiving the first control signal;

a second capacitance having a first terminal coupled for receiving the second control signal;

a first transistor having a first current flowing terminal coupled to a high voltage current source, a second current flowing terminal coupled to a second terminal of the first capacitance, and a control terminal coupled to a second terminal of the second capacitance;

a second transistor having a first current flowing terminal coupled to the high voltage current source, a second current flowing terminal coupled to the second terminal of the second capacitance, and a control terminal coupled to the second terminal of the first capacitance;

wherein the second transistor conducts current when the first control signal is received by the first capacitance;

wherein the first transistor conducts current when the second control signal is received by the second capacitance;

a third transistor having a first current flowing terminal coupled to the high voltage current source, a control terminal coupled to the second terminal of the first capacitance, and a second current flowing terminal;

a fourth transistor having a first current flowing terminal coupled to the second current flowing terminal of the third transistor at a first node, a second current flowing terminal coupled to a ground potential, and a control terminal coupled to the first terminal of the first capacitance;

wherein one of the third or fourth transistor conducts when the first control signal is received by the first capacitance;

wherein the other of the third or fourth transistor conducts when the second control signal is received by the second capacitance;

a fifth transistor having a first current flowing terminal coupled to the high voltage current source, a control terminal coupled to the second terminal of the second capacitance, and a second current flowing terminal;

a sixth transistor having a first current flowing terminal coupled to the second current flowing terminal of the fifth transistor at a second node, a second current flowing terminal coupled to a ground potential, and a control terminal coupled to the first terminal of the second capacitance;

wherein one of the fifth or sixth transistor conducts when the first control signal is received by the first capacitance;

wherein the other of the fifth or sixth transistor conducts when the second control signal is received by the second capacitance;

a third capacitance having a first input terminal coupled to the first node;

a fourth capacitance having a first input terminal coupled to the second node;

a seventh transistor having a first current flowing terminal coupled to a second input terminal of the third capacitance, a second current flowing terminal coupled to the substrate, and a control terminal coupled to a second terminal of the fourth capacitance;

an eighth transistor having a first current flowing terminal coupled to the second input terminal of the fourth capacitance, a second current flowing terminal coupled to the substrate, and a control terminal coupled to the second terminal of the third capacitance;

wherein the seventh transistor conducts current when the fifth transistor conducts;

wherein the eighth transistor conducts when the third transistor conducts;

wherein a voltage at the second input terminal of the fourth capacitance is approximately equal to the substrate voltage when the eighth transistor conducts; and

wherein a voltage at the second input terminal of the fourth capacitance is approximately equal to the substrate voltage plus the voltage of the high voltage current source.

8. The apparatus according to claim 7 further comprising:

a fifth capacitance having a first input terminal coupled to the first input terminal of the fourth capacitance; and

a ninth transistor having a first current flowing terminal coupled to a second input terminal of the fifth capacitance at an output node, a second current flowing terminal coupled to the substrate, and a control terminal coupled to the control terminal of the eighth transistor; and

wherein the ninth transistor conducts current when the third transistor conducts current for causing the output node to be at the substrate voltage.

9. The apparatus according to claim 8 further comprising a tenth transistor having a first current flowing terminal coupled to the second input terminal of the fifth capacitance, a second current flowing terminal coupled to the first current flowing terminal of the ninth transistor, and a control terminal coupled to the control terminal of the ninth transistor;

and

an eleventh transistor having a first current flowing terminal coupled to the high voltage current source, a second current flowing terminal coupled to the first current flowing terminal of the ninth transistor, and a control terminal coupled to the second input terminal of the fifth capacitance.

10. The apparatus according to claim 9 wherein the first control signal comprises a low portion and a high portion, wherein the second control signal comprises a low portion and a high portion, and wherein the low portion of the first control signal is mutually exclusive with the low portion of the second control signal.

11. The apparatus according to claim 10 wherein the first and second transistors each comprise PMOS transistors.

12. The apparatus according to claim 11 wherein the third and fifth transistors each comprise a PMOS transistor and the fourth and sixth transistors each comprise a NMOS transistor.

13. The apparatus according to claim 12 wherein the seventh, eighth, ninth, tenth and eleventh transistors each comprise an NMOS transistor.

14. The apparatus according to claim 13 wherein the low portion of the first and second control signals are each approximately zero volts, and wherein the high portion of the first and second control signals are each approximately 1.5 volts.

15. The apparatus according to claim 14 wherein the high voltage current source is approximately five volts.

16. An apparatus for translating voltages comprising:

a first capacitance having a first terminal coupled for receiving a first control signal;

a second capacitance having a first terminal coupled for receiving a second control signal;

a first transistor and a second transistor having their respective gates and first current-flowing terminals cross-coupled to second terminals of the first and second capacitors, respectively;

wherein each of the control signals comprises a low portion and a high portion, and wherein either the low portion of the first signal is mutually exclusive with the low portion of the second signal or the high portion of the first signal is mutually exclusive with the high portion of the second signal;

a third transistor having a first current flowing terminal coupled to a first voltage, a control terminal coupled to the second terminal of the first capacitance, and a second current flowing terminal;

a fourth transistor having a first current flowing terminal coupled to the second current flowing terminal of the third transistor at a first node;

a second current flowing terminal coupled to a second voltage, wherein the second voltage is less than the first voltage; and

a control terminal coupled to the first terminal of the first capacitance;

wherein one of the third or fourth transistor conducts when the first signal is received by the first capacitance; and

wherein the other of the third or fourth transistor conducts when the second signal is received by the second capacitance.

17. The apparatus of claim 16 wherein the low portion of the first and second control signals are each approximately zero volts, and wherein the high portion of the first and second control signals are each approximately 1.5 volts.

18. The apparatus of claim 17 wherein the first and second transistors each comprise PMOS transistors.

19. The apparatus of claim 18 wherein the third transistor comprises a PMOS transistor and the fourth transistor comprises an NMOS transistor.

20. The apparatus of claim 19 wherein the first voltage is approximately five volts and the second voltage is a ground voltage.

21. The apparatus of claim 16, further comprising:

a fifth transistor having a first current flowing terminal coupled to the first voltage, a control terminal coupled to the second terminal of the second capacitance, and a second current flowing terminal;

a sixth transistor having a first current flowing terminal coupled to the second current flowing terminal of the fifth transistor at a second node, a second current flowing terminal coupled to the second voltage, and a control terminal coupled to the first terminal of the second capacitance;

wherein one of the fifth or sixth transistor conducts when the first control signal is received by the first capacitance;

wherein the other of the fifth or sixth transistor conducts when the second control signal is received by the second capacitance;

a third capacitance having a first terminal coupled to the first node;

a fourth capacitance having a first terminal coupled to the second node;

a seventh transistor having a first current flowing terminal coupled to a second terminal of the third capacitance;

a second current flowing terminal coupled to a third voltage, wherein the third voltage is less than the second voltage; and

a control terminal coupled to a second terminal of the fourth capacitance;

an eighth transistor having a first current flowing terminal coupled to the second terminal of the fourth capacitance, a second current flowing terminal coupled to the third voltage, and a control terminal coupled to the second terminal of the third capacitance;

wherein the seventh transistor conducts current when the fifth transistor conducts;

wherein the eighth transistor conducts current when the third transistor conducts;

wherein a voltage at the second terminal of the fourth capacitance is approximately equal to the third voltage when the eighth transistor conducts; and

wherein a voltage at the second terminal of the fourth capacitance is approximately equal to the third voltage plus the voltage of the high voltage current source.

22. The apparatus of claim 21 wherein the third and fifth transistors each comprise a PMOS transistor and the fourth and sixth transistors each comprise an NMOS transistor.

23. The apparatus of claim 22 wherein the third voltage is a substrate voltage of a substrate.

24. The apparatus of claim 23 wherein the first voltage is approximately five volts and the second voltage is a ground voltage.

25. The apparatus of claim 21 further comprising:

a fifth capacitance having a first terminal coupled to the first terminal of the fourth capacitance; and

a ninth transistor having a first current flowing terminal coupled to a second terminal of the fifth capacitance at an output node, a second current flowing terminal coupled to the third voltage, and a control terminal coupled to the control terminal of the eighth transistor;

wherein the ninth transistor conducts current when the third transistor conducts current for causing the output node to be at a voltage approximately equal to the third voltage.

26. The apparatus of claim 25 further comprising a tenth transistor disposed between the second terminal of the fifth capacitance and the first current flowing terminal of the ninth transistor, the tenth transistor having a first current flowing terminal coupled to the second terminal of the fifth capacitance at the output node, a second current flowing terminal coupled to the first current flowing terminal of the ninth transistor, and a control terminal coupled to the control terminal of the ninth transistor;

and

an eleventh transistor having a first current flowing terminal coupled to the high voltage current source, a second current flowing terminal coupled to the first current flowing terminal of the ninth transistor, and a control terminal coupled to the second terminal of the fifth capacitance.

27. The apparatus of claim 26 wherein the seventh, eighth, ninth, tenth, and eleventh transistors each comprise an NMOS transistor.