Data processor and data processing system

• US 6,327,605 B2
• Filed: 03/19/2001
• Issued: 12/04/2001
• Est. Priority Date: 10/16/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamada, Tetsuya, Totsuka, Yonetaro, Nakagawa, Norio, Arakawa, Fumio
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/810,485
• Publication Number:
  US 20010011291A1
• Time in Patent Office: 260 Days
• Field of Search: 708/501, 708/505, 708/507, 708/524
• US Class Current: 708/501
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/509 for multiple operands, e.g. digital integrators
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/548 Trigonometric functions; Co-ordinate transformations
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.

Claims

1. A data processor comprising:

a unit which executes an inner product operation of 4×

4 in response to one floating point command,

wherein said unit comprises;

an arithmetic block, and

a register file supplying calculation objective data for arithmetic operation to said arithmetic block and being stored a resultant data of an arithmetic operation performed by said arithmetic block,

wherein said arithmetic block comprises;

a function table receiving the calculation objective data from said register file and having function data in accordance with a center value of series expansion corresponding to a value indicative of predetermined bits of the calculation objective data,

an expander for expanding predetermined bits extracted from at least significant bits of the calculation objective data up to a number of bits of the arithmetic block input, the extracted predetermined bits indicating a difference between the calculation objective data and the center value,

four multipliers,

a selector, connected to an output of said expander, an output of said function table and feedback outputs of said multipliers, for selectively supplying one of the outputs from said expander, said function table and said multipliers to said multipliers, and

an adder for adding the outputs from said multipliers.

2. A data processor according to claim 1, wherein said unit further comprises:

a control portion which decodes a command for obtaining a function value for the calculation objective data by polynomial approximation by Tayler expansion,

wherein said control portion provides the calculation objective data to said arithmetic block by register read for the register file, makes calculation of a function value for the calculation objective data according to polynormal approximation to write the result of arithmetic operation to the register file, the polynormal approximation is to calculate the function value corresponding to the calculation objective data by dividing the calculation objective data into a center value and a difference data with respect to the center value, and

a table holding the function value corresponding to the center value required for the polynormal approximation.

3. A data processor according to claim 2, wherein said function is a periodic function, the calculation objective data is divided into upper bits representing the period and lower bits for determining the function value, and the lower bits is divided into the center value and a difference value for the center value.

4. A data processor according to claim 3, wherein the calculation objective data includes angle data and the function includes sine and cosine.

5. A data processor according to claim 4, wherein upper two bits among the lower bits for determining the function value of the angle data indicate a quadrant of the angle, and a function value of other quadrants is obtained by an exchange from sine and cosine of the quadrant to one of a sign reversal and sine or cosine, which compresses the table holding the function value corresponding to the center value into ¼

size.

6. A data processor according to claim 5, wherein said exchange of the sine and cosine is conducted by controlling a selection of registers in said register file for storing the resultant data of arithmetic operation.