Invocation architecture for generally concurrent process resolution

• US 6,327,607 B1
• Filed: 06/25/1999
• Issued: 12/04/2001
• Est. Priority Date: 08/26/1994
• Status: Expired due to Term

• Current Assignee: Wave Semiconductor, Inc.
• Original Assignee: Theseus Research, Inc.
• Inventors: Fant, Karl M.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US09/339,909
• Time in Patent Office: 893 Days
• Field of Search: 707/3, 709/102, 709/105, 709/106, 709/201, 709/202, 709/203, 709/304, 712/25, 712/16, 712/21, 712/1, 712/26, 712/27, 712/201, 712/28, 712/29, 712/30, 712/31, 712/34, 702/14, 364/281, 364/706, 395/706
• US Class Current: 709/201
• CPC Class Codes: G06F 8/31 Programming languages or programming paradigms

Abstract

An invocation architecture for generally concurrent process resolution comprises a plurality of interconnected processors, some of the processors being homogeneous processors and others of the processors being special purpose processors. Each homogeneous processor being capable of invoking a connected processor to have the connected processor resolve instructions. Each processor capable of being invoked by a connected processor to resolve instructions at the invocation of the connected processor.

Claims

1. An invocation architecture for generally concurrent process resolution, comprising:

a plurality of interconnected processors, some of the plurality of interconnected processors being a homogenous processor;

each of the homogeneous processors being capable of creating an invocation for a connected processor to have the connected processor resolve the invocation, the invocation comprising an expression containing sufficient information for a process to proceed;

each of the plurality of interconnected processors being capable of being invoked by a connected processor to resolve invocations;

a plurality of input/output controllers; and

two-way controller global bus connecting each of the homogenous processors to each of the plurality of input/output controllers.

2. The invocation architecture of claim 1, further comprising a special global bus connecting each of the homogenous processors to at least one special purpose processor.

3. The invocation architecture of claim 2, wherein each of the at least one special purpose processor comprises one of a vector processor, a string processor, a logic processor, and a database processor.

4. The invocation architecture of claim 1, further comprising memory global bus connecting each of the plurality of interconnected processors to at least one shared memory.

5. The invocation architecture of claim 4, wherein the at least one shared memory includes a non-replicable definition memory and a result memory.

6. An invocation architecture for generally concurrent process resolution, comprising:

a plurality of interconnected processors, some of the plurality of interconnected processors being a homogenous processor;

each of the homogeneous processors being capable of creating an invocation for a connected processor to have the connected processor resolve the invocation, the invocation comprising an expression containing sufficient information for a process to proceed;

each of the plurality of interconnected processors being capable of being invoked by a connected processor to resolve invocations; and

a two-way memory global bus connecting each of the plurality of interconnected processors to at least one shared memory.

7. The invocation architecture of claim 6, wherein the at least one shared memory includes a non-replicable definition memory and a result memory.

8. The invocation architecture of claim 6, further comprising a special global bus connecting each of the homogenous processors to at least one special purpose processor.

9. The invocation architecture of claim 8, wherein each of the at least one special purpose processor comprises one of a vector processor, a string processor, a logic processor, and a database processor.

10. The invocation architecture of claim 8, wherein each of the at least one special purpose processor comprises one of a vector processor, a string processor, a logic processor, and a database processor.

11. The invocation architecture of claim 10, wherein each of the at least one special purpose processor comprises one of a vector processor, a string processor, a logic processor, and a data base processor.