Parallel access virtual channel memory system

• US 6,327,642 B1
• Filed: 11/10/1999
• Issued: 12/04/2001
• Est. Priority Date: 11/18/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Incorporated (NEC Corporation)
• Inventors: Ando, Manabu, Lee, Jeffery H.
• Primary Examiner(s): Peikari, B. James
• Application Number:
  US09/437,810
• Time in Patent Office: 755 Days
• Field of Search: 710/31, 710/38, 711/5, 711/119, 711/120, 711/123, 711/125, 711/126, 711/128, 711/137, 711/138, 711/145, 711/203, 711/204, 711/106, 711/148, 711/149, 711/150, 365/203, 365/222
• US Class Current: 711/120
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches

Abstract

A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include, interfaces, cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is independently addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Claims

1. A memory system comprising:

a first interface circuit for coupling the memory system to one or more external memory masters, wherein the first interface circuit receives address and data information from the memory masters;

a first bus coupled to the interface circuit for receiving address and data information from the first interface circuit;

a main memory array including a plurality of memory banks;

a second bus coupled to the main memory array, wherein the second bus receives data values read from the main memory array;

a bus bypass circuit which couples the first bus to the second bus;

a plurality of cache memory arrays connected in parallel between the first bus and the second bus, wherein each of the cache memory arrays receives data information from the first bus and the second bus;

a plurality of cache address arrays connected in parallel between the first bus and the second bus, wherein each of the cache address arrays receives address information from the first bus, each of the cache address arrays further being coupled to a corresponding one of the cache memory arrays, wherein each cache address array and corresponding cache memory array form a virtual cache channel which is independently addressable by the one or more memory masters and which accesses any of the plurality of memory banks of the main memory array.

2. The memory system of claim 1, wherein the memory array has a first data width and the second bus has a second data width, the memory system further comprising a memory interface circuit wherein the memory interface circuit performs a multiplexing function for data passing between the memory arrays and the second bus.

3. The memory system of claim 2, wherein the first data width is greater than the second data width.

4. The memory system of claim 2, wherein the first data width is less than the second data width.

5. The memory system of claim 1, further comprising a plurality of cache interface circuits wherein each cache interface circuit is coupled between the second bus and a corresponding cache memory array, wherein the cache interface circuits are controlled to pass data to selected cache memory arrays.

6. The memory system of claim 1, further comprising a plurality of cache interface circuits, wherein each cache interface circuit is coupled between the first bus and a corresponding cache memory array, wherein the cache interface circuits are controlled to pass data from selected cache memory arrays to the first bus when a current access address provided by a memory master matches an address stored in a cache address array.

7. The memory system of claim 1, wherein each cache memory array comprises a plurality of cache entries and each cache address array comprises a corresponding plurality of cache addresses.