Encapsulation of microelectronic assemblies

• US 6,329,224 B1
• Filed: 04/28/1998
• Issued: 12/11/2001
• Est. Priority Date: 04/28/1998
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Mitchell, Craig S., Nguyen, Tan, Distefano, Thomas H.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): ROCCHEGIANI, RENZO
• Application Number:
  US09/067,698
• Time in Patent Office: 1,323 Days
• Field of Search: 438/29, 438/126, 438/127, 438/128, 438/FOR.367, 438/111, 438/112, 438/113, 438/114
• US Class Current: 438/127
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Claims

1. A method of encapsulating a plurality of microelectronic assemblies having oppositely-facing top and bottom surfaces comprising the steps of:

(a) providing said assemblies within an opening in a frame having top and bottom surfaces, and providing top and bottom sealing layers sealingly connected to the frame extending across the opening of the frame, said top and bottom sealing layers defining an enclosed space encompassing said assemblies;

(b) engaging the frame, sealing layers and assemblies between top and bottom fixture elements; and

(c) injecting a liquid encapsulant between the sealing layers and around the assemblies while the frame, sealing layer and assemblies are engaged between the top and bottom fixture elements, said sealing layers and frame containing the liquid encapsulant; and

(d) curing the liquid encapsulant.

2. A method as claimed in claim 1 further comprising the step of removing the assemblies from the frame.

3. A method as claimed in claim 2 wherein the frame is destroyed in removing the assemblies from the frame.

4. A method as claimed in claim 3 further comprising repeating the aforesaid steps using a new frame and assemblies in each repetition.

5. A method as claimed in claim 1 further comprising the step of removing said frame, sealing layers and assemblies from the fixture before said curing step, said sealing layers and frame confining said encapsulant during said injecting step.

6. A method as claimed in claim 5 wherein said curing step is performed at an elevated temperature.

7. A method as claimed in claim 6 wherein said frame is formed form a material selected from the group consisting of polymeric materials, fibrous materials and combinations thereof.

8. A method as claimed in claim 1 further comprising evacuating a space between said sealing layers and around said assemblies prior to the step of injecting said encapsulant.

9. A method as claimed in claim 8 wherein said injecting step includes the steps of advancing a hollow needle through a hole in one of said sealing layers so that said needle is in communication with said enclosed space between said sealing layers and passing the encapsulant into said enclosed space through said hollow needle.

10. A method as claimed in claim 9 wherein said evacuating step is performed by applying a vacuum through said hole.

11. A method as claimed in claim 10 wherein said step of applying a vacuum through said hole is performed by applying a vacuum to a passage in one of said fixture elements communicating with said hole while said needle is not in said hole.

12. A method as claimed in claim 11 further comprising the step of sealing said one of said fixture elements to the sealing layer having said hole by squeezing a resilient gasket surrounding said hole between the sealing layer and said one of said fixture elements.

13. A method as claimed in claim 12 wherein said frame supports the sealing layer having said hole in the vicinity of said hole.

14. A method as claimed in claim 11 wherein said step of advancing a needle is performed by advancing the needle through said passage in said one of said fixture elements.

15. A method as claimed in claim 14 wherein said sealing layer sealingly engages the needle at said hole during said step of passing the encapsulant into the space through said hollow needle.

16. A method as claimed in claim 1 wherein said assemblies have porous regions and wherein said encapsulant penetrates into said porous regions during said injecting step.

17. A method as claimed in claim 1 wherein said step of providing said assemblies, frame and sealing layer includes the step of attaching a plurality of semiconductor chips to a unitary tape and electrically connecting said chips to terminals exposed at a surface of said tape so as to provide a plurality of semiconductor chip assemblies, each including one or more of said chips and a region of the tape associated therewith.

18. A method as claimed in claim 17 wherein said step of providing said assemblies, frame and sealing layer further includes the step of providing a cover layer separate from said tape and applying said cover layer on said surface of said tape, so that said tape and said cover layer cooperatively constitute one said sealing layer.

19. A method as claimed in claim 17 wherein one said sealing layer includes said tape, and wherein said step of providing said assemblies, frame and sealing layer includes the step of sealing the tape to the frame.

20. A method as claimed in claim 17 wherein said step of attaching chips to the tape is performed so that front surfaces of said chips bearing said contacts face towards said tape, said tape forming the top surfaces of said assemblies.

21. A method as claimed in claim 20 wherein said step of providing said assemblies, frame and sealing layer includes the step of applying said bottom sealing layer on rear surfaces of said chips.

22. A method as claimed in claim 20 wherein said step of providing said assemblies, frame and sealing layer includes the step of applying said bottom sealing layer spaced from rear surfaces of said chips, so that said encapsulant will cover said rear surfaces during said step of injecting said encapsulant.

23. A method as claimed in claim 17 wherein said step of attaching chips to the tape is performed so that front surfaces of said chips bearing said contacts face away from said tape and rear surfaces of the chips face toward the tape, said tape forming the bottom surfaces of said assemblies, said top sealing layer overlying said front surfaces of said chips.

24. A method as claimed in claim 23 wherein said top sealing layer is spaced above said front surfaces of said chips so that said encapsulant flows between said front surfaces of said chips and said top sealing layer during said step of injecting said encapsulant.

25. A method as claimed in claim 23 wherein said chips include optically active elements adapted to interact with light in a band of wavelengths, and wherein said top sealing layer is transparent to light in such band of wavelengths, the method further comprising the steps of removing said assemblies from said frame so that a portion of said top sealing layer remains with each said assembly.

26. A method as claimed in claim 25 wherein said top sealing layer includes refractive elements adapted to refract light in said band of wavelengths.

27. A method as claimed in claim 23 wherein said top sealing layer is thermally conductive, the method further comprising the steps of removing said assemblies from said frame so that a portion of said top sealing layer remains with each said assembly.

28. A method as claimed in claim 17 wherein said steps of attaching said chips and electrically connecting said chips are performed while said tape is mounted on said frame.

29. A method as claimed in claim 28 further comprising the step of providing porous structures between said chips and said tape, said encapsulant filling said porous structures during said injecting step.

30. A method as claimed in claim 29 wherein said step of providing said porous structures includes the step of applying compliant pads to said tape while said tape is mounted on said frame.

31. A method as claimed in claim 28 wherein said tape has openings therein, said step of electrically connecting said chips to said terminals including performing operations through said openings, said top sealing layer sealing said openings.

32. A method as claimed in claim 1 wherein said step of providing said assemblies, frame and sealing layers includes the step of attaching a plurality of semiconductor chips to a bottom sealing layer having a plurality of vertically-extending walls formed therein and defining pockets so that said chips are lodged in said pockets, said walls at least partially surrounding each chip after completion of the process so that said walls serve as protective packaging for the chip.

33. A method as claimed in claim 1 wherein said step of engaging the frame, sealing layers and assemblies between top and bottom elements of a fixture includes the step of squeezing a resilient top gasket between the top element of the fixture and a portion of the top sealing layer overlying the frame, and squeezing a resilient bottom gasket between the bottom element of the fixture and a portion of the bottom sealing layer overlying the frame.

34. A method as claimed in claim 1 further comprising the step of urging a floating plate on one of said elements towards the other one of said elements so that said assemblies and regions of the sealing layers within the aperture of the frame overlying said assemblies are squeezed between the floating plate and said other one of said elements.

35. A method as claimed in claim 34 wherein said step of urging said floating plate toward the other one of said elements is performed during the step of injecting the encapsulant.

36. A method as claimed in claim 1 wherein one said sealing layer is formed from a metallic material, and wherein a portion of the metallic sealing layer remains attached to each said assembly after completion of the process, so that such portion of the sealing layer acts as a heat transfer element for the completed assembly.

37. A method of fabricating a plurality of semiconductor chip assemblies comprising the steps of:

(a) attaching a plurality of semiconductor chips to a bottom surface of a unitary tape and electrically connecting said chips to terminals exposed at a top surface of said tape while said tape is held on a frame so as to provide a plurality of semiconductor chip assemblies, each including one or more of said chips and a region of the tape associated therewith, said chips being disposed in an aperture enclosed by said frame;

(b) applying a top sealing layer on said top surface of said tape and on a top surface of the frame;

(c) applying a bottom sealing layer on bottom surfaces of said chips facing away from said tape and on a bottom surface of said frame; and

(d) injecting a liquid encapsulant around said chips so that the encapsulant contacts the chips and the tape; and

(e) curing the encapsulant, said frame and said sealing layers confining said encapsulant during said curing step and preventing said encapsulant from contacting the bottom surfaces of the chips and the top surface of the tape.

38. A method as claimed in claim 37 further comprising the step of evacuating a space between said sealing layers around said chips prior to said injecting step.