×

Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow

  • US 6,329,234 B1
  • Filed: 07/24/2000
  • Issued: 12/11/2001
  • Est. Priority Date: 07/24/2000
  • Status: Expired due to Term
First Claim
Patent Images

1. A method for fabricating IC'"'"'s comprising:

  • providing a substrate having a layer of dielectric;

    providing a first level conductor wiring surrounded by barrier material within the said layer of dielectric;

    depositing a metal protect buffer layer over said first level of conductor wiring;

    depositing an intermetal dielectric (IMD) layer over said metal protect buffer layer;

    patterning and etching MIM/Inductor damascene openings in said intermetal dielectric (IMD) layer and etching to said metal protect buffer layer;

    removing the patterning and masking material and removing the exposed metal protect buffer layer;

    depositing an insulating protect buffer layer over the patterned intermetal dielectric (IMD) layer and over said first level of conductor wiring;

    depositing an MIM insulating layer over said insulating protect buffer layer;

    depositing a conducting metal buffer layer over said MIM insulating layer;

    patterning and etching dual damascene via/trench openings, or trench/via openings by process reversal, in said intermetal dielectric (IMD) layer and removing all patterning and masking material exposing all openings;

    forming conducting metal over said via/trench openings and polishing off excess conducting metal and excess conducting metal protect buffer layer.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×