High density flip chip memory arrays

• US 6,329,712 B1
• Filed: 03/25/1998
• Issued: 12/11/2001
• Est. Priority Date: 03/25/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Wood, Alan G., Akram, Salman
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/047,796
• Time in Patent Office: 1,357 Days
• Field of Search: 257/778, 257/738, 257/737, 257/734, 257/728, 257/692, 257/693, 257/690, 257/758, 257/700, 257/701, 257/209, 257/202, 257/784, 257/786, 365/51, 365/230.03, 365/63
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/556 against alpha rays
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures

Abstract

A low alpha emissivity-induced error solder bump, flip chip integrated circuit device. The device includes a semiconductor die having an active surface and a bond pad array disposed about the active surface of the die. The active surface of the die includes logic circuits adjacent memory cell arrays. Each of the bond pads directly overlays a logic circuit, to which they may be connected. The present invention also includes methods for designing and fabricating the invented devices and connecting them to a carrier substrate.

Claims

1. An integrated circuit device, comprising:

a semiconductor die having an active surface including at least one memory cell array and at least one logic circuit element comprising at least one of a column decoder and a row decoder positioned adjacent to at least one memory cell of said at least one memory cell array and carried by said semiconductor die; and

an array of bond pads on said active surface of said semiconductor die, at least a portion of at least one bond pad of said array of bond pads being located vertically over said at least one logic circuit element.

2. The integrated circuit device according to claim 1, wherein said at least one bond pad is operatively connected with said at least one logic circuit element.

3. The integrated circuit device according to claim 2, wherein said at least one bond pad is in direct contact with said at least one logic circuit element.

4. The integrated circuit device according to claim 1, wherein said at least one bond pad is laterally offset from said at least one memory cell array.

5. The integrated circuit device according to claim 1, wherein the integrated circuit device comprises a dynamic random access memory integrated circuit.

6. The integrated circuit device according to claim 1, further comprising a discrete external connective element in electronic communication with said at least one bond pad.

7. The integrated circuit device according to claim 6, further comprising an encapsulant, said encapsulant covering said at least one memory cell array and said at least one logic circuit element.

8. The integrated circuit device according to claim 7, wherein said encapsulant covers all external surfaces of said semiconductor die, but for said discrete external connective element.

9. A dynamic random access memory integrated circuit device, comprising:

a die having an active surface bearing a plurality of memory cell arrays and a plurality of logic circuit elements, each of said plurality of logic circuit elements comprising at least one of a column decoder and a row decoder; and

a plurality of bond pads located on said active surface of said die, each of said plurality of bond pads being associated with a corresponding one of said plurality of logic circuit elements, each of said plurality of bond pads directly overlying a corresponding logic circuit element of said plurality.

10. The dynamic random access memory integrated circuit device according to claim 9, wherein said each of said plurality of bond pads is disposed over its associated logic circuit element.

11. The dynamic random access memory integrated circuit device according to claim 9, further comprising a plurality of discrete external connective elements, each being in electrical communication with an underlying bond pad, wherein at least a portion of the integrated circuit device is encapsulated with an encapsulant through which each of said plurality of discrete connective elements extends.

12. The dynamic random access memory integrated circuit device according to claim 11, wherein said encapsulant covers said plurality of memory cell arrays and said plurality of logic circuit elements.

13. The dynamic random access memory integrated circuit device according to claim 11, wherein said encapsulant covers all external surfaces of said die.

14. An integrated circuit device, comprising:

a semiconductor die including an active surface, a memory cell array and a logic circuit element positioned between adjacent memory cells of said memory cell array; and

at least one bond pad located on said active surface of said semiconductor die, at least a portion of said at least one bond pad being positioned at least partially vertically over said logic circuit element.

15. The integrated circuit device according to claim 14, wherein said at least one bond pad is operatively connected with said logic circuit element.

16. The integrated circuit device according to claim 15, wherein said at least one bond pad directly overlies said logic circuit element.

17. The integrated circuit device according to claim 14, wherein said at least one bond pad is laterally offset from said memory cell array.

18. The integrated circuit device according to claim 14, wherein the integrated circuit device is a dynamic random access memory integrated circuit.

19. The integrated circuit device according to claim 14, further comprising a discrete external connective element formed over and in electrical communication with said at least one bond pad.

20. The integrated circuit device according to claim 19, further comprising an encapsulant covering said memory cell array and said logic circuit element with said discrete external connective element extending through said encapsulant.

21. The integrated circuit device according to claim 20, wherein said encapsulant covers all external surfaces of said semiconductor die.

22. A flip chip DRAM, comprising:

a die including a memory cell array and at least one logic circuit element comprising at least one of a column decoder and a row decoder; and

at least one discrete external connective element disposed on an active surface of said die, at least a portion of said at least one discrete external connective element being positioned vertically over said at least one logic circuit element.

23. The flip chip DRAM of claim 22, wherein said at least one discrete external connective element is laterally offset from memory cells of said memory cell array.

24. The flip chip DRAM of claim 22, further comprising at least one bond pad at least partially positioned vertically over said at least one logic circuit element.

25. The flip chip DRAM of claim 24, wherein said at least one discrete external connective element is disposed on said at least one bond pad.

26. The flip chip DRAM of claim 25, wherein said at least one bond pad operatively connects said at least one discrete external connective element to said at least one logic circuit element.

27. A memory device, comprising:

at substrate;

at least one active memory element on said substrate;

at least one active non-memory circuit comprising at least one of a column decoder and a row decoder carried by said substrate laterally adjacent said at least one active memory element; and

at least one electrically conductive bump disposed on said substrate substantially vertically over said at least one active non-memory circuit.

28. The memory device of claim 27, further comprising at least one bond pad formed over said at least one active non-memory circuit.

29. The memory device of claim 28, wherein said at least one electrically conductive bump is formed on said at least one bond pad.

30. The memory device of claim 28, wherein said at least one bond pad operatively connects said at least one active non-memory circuit to said at least one electrically conductive bump.

31. The memory device of claim 27, wherein said at least one electrically conductive bump is laterally offset from said at least one active memory element.

32. A DRAM, comprising:

a substrate;

at least one memory cell on said substrate;

at least one logic circuit element comprising at least one of a column decoder and a row decoder on said substrate, adjacent and in communication with said at least one memory cell; and

at least one bond pad disposed on said substrate and at least partially vertically over said at least one logic circuit element.

33. The DRAM of claim 32, wherein said at least one bond pad is laterally offset from said at least one memory cell.

34. The DRAM of claim 32, further comprising at least one electrically conductive bump disposed on said at least one bond pad.

35. A memory device, comprising:

a substrate;

at least one active memory element on said substrate;

at least one active non-memory circuit comprising at least one of a column decoder and a row decoder on said substrate, adjacent said at least one active memory element; and

at least one bond pad disposed on said substrate, at least a portion of said at least one bond pad being positioned vertically over said at least one active non-memory circuit.

36. The memory device of claim 35, wherein said at least one bond pad is laterally offset from said at least one active memory element.

37. The memory device of claim 35, further comprising at least one discrete external connective element disposed on said at least one bond pad.