Method and apparatus for reliability testing of integrated circuit structures and devices

• US 6,329,831 B1
• Filed: 08/08/1997
• Issued: 12/11/2001
• Est. Priority Date: 08/08/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Bui, Nguyen Duc, Niederhofer, Michael Anthony, Pham, Van Hung
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US08/908,794
• Time in Patent Office: 1,586 Days
• Field of Search: 324/765, 324/760, 324/763, 165/80.3, 165/80.4
• US Class Current: 324/750.03
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

A method and apparatus for monitoring and controlling integrated circuit devices-under-test (DUTS). A preferred embodiment includes a computer based controller, a temperature control module, a power supply controller, a chamber interface module, a driver card and a DUT board. The computer-based controller responding to preprogrammed instructions (software) operates and coordinates the temperature control module, the chamber interface module, the power supply controller, and the driver card. The driver card, receiving commands and data from the computer-based controller, sends and receives a number of signals to and from the DUTs on the DUT board. These signals include voltage sources for operating the DUTs, a load voltage, DC current sources for setting duty and frequency cycles, switch signals, voltage measurement signals, and resistance measurement signals. The DUT board is a printed circuit board for holding a number of DUTs. Each of the DUTs is an integrated circuit containing one or more sets of circuitry for testing specifically designed test structures.

Claims

1. A system for testing integrated circuit devices and controlling and monitoring said integrated circuit devices-under tests (DUTs), comprising:

a test chamber for creating stress conditions to test DUTs;

a chamber controller communicatively connected to said test chamber for controlling stress conditions in said test chamber in response to chamber control signals, said chamber controller comprising a temperature controller for modifying the temperature in said test chamber and a chamber interface controller for controlling the electromagnetic field level in said test chamber;

a DUT board having one or more DUTs disposed thereon;

a driver card communicatively connected to said DUT board for operating and monitoring said DUTs on said DUT board;

an adjustable power supply;

a power supply controller for controlling power from said adjustable power supply to said driver card and to said DUT board;

a computer for providing control signals to said chamber controller, said power supply controller, and said driver card in operating said test chamber and said DUTs and in monitoring the performance of said DUTs; and

whereby said computer operates said chamber controller to dynamically vary the temperature and control the electromagnetic field in said test chamber and generates signals to said DUTs to test and monitor said DUTs.

2. A system as recited in claim 1 wherein said DUT board includes

a circuit board;

a connector disposed on said circuit board;

a data bus disposed on said circuit board and communicatively connected to said connector; and

one or more of said DUTs disposed on said circuit board and being communicatively connected to said data bus for receiving one or more DUT control signals and for providing signals generated in response to said DUT control signals.

3. A system as recited in claim 2 where said DUT board further includes an auxiliary circuit disposed between each of said DUTs and said data bus for controlling and conditioning the signals to and from said data bus and said DUTs.

4. A system as recited in claim 3 wherein said auxiliary circuit includes at least one transistor switch for selectively establishing the connections for measuring the DUTs.

5. A system as recited in claim 1 wherein said driver card includes:

an external data bus for receiving instructions and data from said computer;

a buffer for storing said instructions and data;

a decoder for executing and routing said instructions and data from said buffer;

a programmable voltage controller responsive to said instructions and data and operative to control a voltage regulator for delivering voltage supply to said DUTs;

a programmable duty and frequency controller responsive to said instructions and data and operative to control said DUTs; and

a measurement circuit for measuring said DUT'"'"'s and providing measured signals to said computer.

6. A system as recited in claim 5 wherein said measurement circuit further comprises:

a switch controller for selectively establishing the connections for measuring a selected DUT; and

a multiplexer for selecting said selected DUT for receiving a measured signal representative of a characteristic of the test structure of said selected DUT.

7. A system as recited in claim 6 wherein said measurement circuit further includes a reference current source controller for providing a reference current to said selected DUT in measuring said selected DUT.

8. A system as recited in claim 5 wherein said driver card further includes a gate controller for controlling the delivery of a voltage potential for biasing said DUTs.

9. A system as recited in claim 5 wherein said driver card further includes a mode register for placing said driver card in a test mode or a measurement mode.

10. A system as recited in claim 1 wherein the control signals for operating said DUTs are DC signals.

11. A system as recited in claim 1 wherein each of said DUTs includes:

an oscillator for receiving a DUT control signal and generating an AC signal having a frequency corresponding to said DUT control signal; and

a test structure having at least two measurable ends for testing and measuring the characteristics of said test structure, one of said measurable ends connected to said oscillator.

12. A system as recited in claim 11 wherein each test structure is connected to a biasing voltage source.

13. A system as recited in claim 11 wherein each of said DUTs further includes an amplifier for amplifying said AC signal for the test structure.

14. A system as recited in claim 2 wherein said DUT control signals are DC signals.

15. A system as recited in claim 5 wherein said programmable duty and frequency controller operates said DUTs by providing DC signals at specified levels.

21. A system as recited in claim 5 wherein said driver card further includes a programmable voltage regulator for providing a voltage potential for biasing said DUTs.

16. A method for examining test structures within integrated circuits devices-under-test (DUTs) under dynamically varying environmental conditions, comprising the steps of:

placing a DUT board having one or more DUTs disposed thereon in a test chamber;

adjusting environmental conditions including temperature and an electromagnetic field within said test chamber to predefined levels; and

operating the test structures within a DUT by providing one or more DC control signals to said DUT, said DC control signals causing an excitation signal to be applied to the test structure of said DUT under the control of a computer.

17. A method as recited in claim 16 further including the step of measuring the response of the test structure of said DUT in response to said excitation signal.

18. A semiconductor test circuit, comprising:

an oscillator for receiving one or more DC control signals and for generating an AC signal having a frequency level and a duty cycle corresponding to said DC control signals; and

a test structure having a first measurable end and a second measurable end for testing and measuring the characteristics of said test structure, said first measurable end receiving said AC signal from said oscillator.

19. A semiconductor test circuit as recited in claim 18 wherein said second measurable end of said test structure is connected to a biasing voltage source.

20. A semiconductor test circuit as recited in claim 18 wherein said second measurable end of said test structure receives a load voltage for biasing said test structure.