N-way circular phase interpolator for generating a signal having arbitrary phase

• US 6,329,859 B1
• Filed: 03/23/2000
• Issued: 12/11/2001
• Est. Priority Date: 03/23/2000
• Status: Expired due to Fees

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: BitBlitz Communications, Inc. (Renesas Electronics Corporation)
• Inventors: Wu, Bin
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US09/535,270
• Time in Patent Office: 628 Days
• Field of Search: 327/116, 327/119-122, 327/237, 327/246, 327/250, 327/291, 327/295, 327/270, 327/271, 327/274, 327/276, 327/277, 327/278
• US Class Current: 327/291
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/131 Digitally controlled

Abstract

An N-way Circular Phase Interpolator interpolates the N phases of a reference clock signal to generate a tunable clock. By using more than two phases for interpolation, high excess frequencies as well as high precision (i.e. small jitter) are achieved. The N-way Circular Phase Interpolator provides for analog filtering in the phase domain, which attenuates the out-of-band phase noises thus further reducing the output jitter.

Claims

1. A circular phase interpolator for generating a clock having a phase and comprising:

a multiplexer for receiving a plurality of signals representative of evenly spaced phases of a reference clock and in response thereto supplying at least three input phases;

input ports for receiving the at least three input phases each phase being representative of a different one of the phases of the reference clock;

input ports for receiving at least three input weight signals; and

circuitry for applying each of the at least three input weight signals to a different one of the at least three input phases thereby forming a weighted sum of the at least three input phases, which sum represents the phase of the generated clock.

2. The circular phase interpolator of claim 1 further comprising at least three digital-to-analog signal converters each for receiving and converting to an analog signal a digital signal of each of the at least three input weight signals.

3. The circular phase interpolator of claim 2 further comprising at least three low-pass analog filters for respectively low-pass filtering a different one of the at least three converted analog signals.

4. The circular phase interpolator of claim 3 wherein said circuitry comprises a linear phase interpolator for forming the weighted sum.

5. The circular phase interpolator of claim 4 further comprising a combinational logic for receiving m bits and in response thereto supplying digital signals received by the at least three digital-to-analog signal converters.

6. The circular phase interpolator of claim 5 wherein said evenly spaced phases of the reference clock are respectively positioned at 0°

, 60°

, 120°

, 180°

, 240° and

300°

of a 360°

phase.

7. The circular phase interpolator of claim 6 wherein a first and a second input phase of the at least three input phases represent reference clock phases having 60°

phase difference and wherein the second and a third input phase of the at least three input phases represent reference clock signal phases having 60°

phase difference.

8. The circular phase interpolator of claim 7 wherein the input weight signal applied to the third input phase is zero.

9. The circular phase interpolator of claim 8 wherein as the interpolated phase moves from a region between 0°

and 30°

of the first and second input phases to a region between 30° and

60°

of the first and second input phases, the third input phase changes from being 60°

apart from one of the first and second input phases to being 60°

apart from the other of the first and second input phases.

10. The circular phase interpolator of claim 9 wherein as the interpolated phase increases above the second phase or decreases below the first phase, the input weights are redistributed so that no glitch is generated at the linearly interpolated phase.

11. The circular phase interpolator of claim 10 wherein the weighted sum is a linear weighted sum of the at least three input phases.

12. The circular phase interpolator of claim 11 wherein the linearly interpolated phase is proportional to the convolution of the unit sample response of any one of the at least three analog filters and a digital word whose most significant bits are the signals applied to input select terminals of the multiplexer and whose least significant bits are the m bits applied to the combinational logic.

13. The circular phase interpolator of claim 1 wherein the weighted sum is a non-linear weighted sum of the at least three input phases.

14. A method for generating a clock having a phase, said method comprising:

receiving a plurality of evenly spaced phases of a reference clock;

receiving a plurality of control signals;

choosing at least three input phases from the plurality of evenly spaced phases of the reference clock based on the control signals;

supplying the at least three input phases;

receiving the at least three input phases, each phase being representative of a different one of phases of the reference clock;

receiving at least three input weight signals; and

applying each of the at least three input weight signals to a different one of the at least three input phases thereby forming a weighted sum of the at least three input phases, which sum represents the phase of the generated clock.

15. The method of claim 14 further comprising converting each of the at least three weight signals from a digital signal to an analog signal.

16. The method of claim 15 further comprising low-pass filtering each of the at least three converted analog signals.

17. The method of claim 16 further comprising receiving m bits and in response thereto supplying digital signals for converting each of the at least three weight signals from a digital signal to an analog signal.

18. The method of claim 17 wherein the act of receiving a plurality of evenly spaced phases of the reference clock includes receiving evenly spaced phases 0°

, 60°

, 120°

, 180°

, 240° and

300°

of the reference clock.

19. The method of claim 18 wherein the act of receiving the at least three input phases includes receiving first and second phases having 60°

phase difference and receiving a third phase having 60°

phase difference with respect to the second phase.

20. The method of claim 19 wherein a third input weight signal of the at least three input weight signals is zero.

21. The method of claim 20 wherein as the interpolated phase moves from a region between 0°

and 30°

of the received first and second input phases to a region between 30° and

60°

of the received first and second input phases, the third input phase changes from being 60°

apart from one of the first and second input phases to being 60°

apart from the other of the first and second input phases.

22. The method of claim 21 wherein as the interpolated phase increases above the second phase or decreases below the first phase, the input weights are redistributed so that no glitch is generated at the interpolated phase.

23. The method of claim 14 wherein the weighted sum is a linear weighted sum of the at least three input phases.

24. The method of claim 14 wherein the weighted sum is a non-linear weighted sum of the at least three input phases.