Semiconductor storage device

• US 6,330,198 B1
• Filed: 06/08/2000
• Issued: 12/11/2001
• Est. Priority Date: 06/09/1999
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Koshikawa, Yasuji
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/590,239
• Time in Patent Office: 551 Days
• Field of Search: 365/200, 365/230.06, 365/230.02
• US Class Current: 365/200
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A semiconductor storage device can improve probability of relieving of defective cell. The semiconductor storage device includes a redundancy cell for relieving a defective cell when the defective cell is found during fabrication process of a memory cell, a redundancy judgment circuit making judgment whether an input address is a column address of the defective cell or not and redundancy column selection lines for making the redundancy cell active when the redundancy judgment circuit makes judgment that the input address is the column address of the defective cell. The semiconductor storage device further includes means for dividing the redundancy cell connected to one redundancy column selection line into a plurality of divided redundancy cells and assigning the column address of the defective cell to each of divided redundancy cells as relieving address.

Claims

1. A semiconductor storage device comprising:

a redundancy cell for relieving a defective cell when the defective cell is found during fabrication process of a memory cell;

a redundancy judgment circuit making judgment whether an input address is a column address of said defective cell or not;

redundancy column selection lines for making said redundancy cell active when said redundancy judgment circuit makes judgment that said input address is said column address of said defective cell;

means for dividing said redundancy cell connected to one redundancy column selection line into a plurality of divided redundancy cells and assigning the column address of said defective cell to each of divided redundancy cells as relieving address.

2. A semiconductor storage device as set forth in claim 1, wherein a plurality of said redundancy judgment circuits are provided for making judgment whether said input address is said relieving address assigned for each of said divided redundancy cell.

3. A semiconductor storage device as set forth in claim 2, which further comprises logic operation means for performing logical operation for respective outputs of a plurality of said redundancy judgment circuits and means for selecting any one of a plurality of redundancy column lines depending upon a result of operation of said logic operation means.

4. A semiconductor storage device as set forth in claim 3, wherein said logic operation means performs operation of logical sum of outputs of said plurality of redundancy judgment circuits.

5. A semiconductor storage device as set forth in claim 1, which further comprises means for switching between input/output line of said redundancy cell in said memory cell and normal input/output line depending upon a result of judgment by said redundancy judgment circuit.

6. A semiconductor storage device as set forth in claim 5, wherein said switching means is constructed for switching said input/output line of said redundancy cell and said input/output line of said normal cell.

7. A semiconductor storage device as set forth in claim 5, which is constructed to select the column selection line of said normal cell irrespective of the result of judgment of said redundancy judgment circuit.

8. A semiconductor storage device as set forth in claim 1, wherein said plurality of redundancy judgment circuits are provided corresponding to number of division of said redundancy cell.

9. A semiconductor storage device as set forth in claim 8, when said redundancy cell is divided into two, said redundancy judgment circuit in number of double of said redundancy column selection lines are provided.

10. A semiconductor storage device as set forth in claim 8, when said redundancy cell is divided into four, said redundancy judgment circuit in number of four times of said redundancy column selection lines are provided.

11. A semiconductor storage device as set forth in claim 3, wherein said means for selecting one of said plurality of redundancy column selection lines comprises a buffer circuit for driving selected redundancy column selection line.