High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network

• US 6,330,591 B1
• Filed: 03/09/1998
• Issued: 12/11/2001
• Est. Priority Date: 03/09/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Ducaroir, Francois, Jenkins, Michael O., Nakamura, Karl S.
• Primary Examiner(s): Peikari, B. James
• Application Number:
  US09/036,897
• Time in Patent Office: 1,373 Days
• Field of Search: 711/141, 711/146, 711/130, 711/124, 709/200, 709/213, 709/214, 709/216, 709/217, 709/218, 709/219, 710/65, 710/71
• US Class Current: 709/213
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0817 using directory methods

Abstract

One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent. Each transmit unit comprises a receiver operably coupled between an input port and an output port, and a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. Also included are a transmitter which receives parallel data and transmits a serial data stream. The parallel data are received concurrently with the serialized data being received. A deserializer is coupled to convert the serialized data into the deserialized data. A serializer is coupled to convert the parallel data into the serial data stream.

Claims

1. A computer system, comprising:

a first central processing unit (CPU) operably coupled to access a first cluster cache via a first cluster cache controller, wherein the first cluster cache is coupled to a first I/O subsystem through a path not including a first system bus coupled between the first CPU and the first cluster cache;

a second central processing unit (CPU) operably coupled to access a second cluster cache via a second cluster cache controller, wherein the second cluster cache is coupled to a second I/O subsystem through a path not including a second system bus coupled between the second CPU and the second cluster cache;

a differential serial line, adapted to transfer data between the first and second cluster cache controllers; and

a directory, operably coupled to the first and second cluster cache controllers via the differential serial line, and providing information on whether a most recent version of data requested by either CPU is present in either cluster cache.

2. The computer system as recited in claim 1, wherein the information in the directory further comprises cluster cache contents or status.

3. The computer system as recited in claim 2, wherein the cluster cache status comprises “

modified”

, “

exclusive”

, “

shared” and

“

invalid”

states, which are attributes of cached data according to a modified MESI cache management algorithm.

4. The computer system as recited in claim 1, wherein the first CPU is adapted to seek data in the first cluster cache before seeking it in the second cluster cache.

5. The computer system as recited in claim 1, further comprising individual directories associated with both the first and second CPUs, such that each directory provides information on whether a most recent version of data requested by either CPU is present in either cluster cache.

6. The computer system as recited in claim 5, wherein information in either directory may be transmitted via the differential serial line to the other directory.

7. The computer system as recited in claim 1, wherein each CPU is operably coupled to a memory subsystem, to its respective cluster cache, and to an I/O subsystem by a system bus.

8. The computer system as recited in claim 7, wherein the memory subsystem comprises a local cache.

9. The computer system as recited in claim 1, wherein the directory is within the first cluster cache controller.

10. The computer system as recited in claim 1, further comprising a serial transfer unit, operably coupled to each cluster cache controller, wherein said serial transfer units are adapted to convert between parallel and serial data format, and are adapted to drive serial data upon the differential serial line and receive serial data from the differential serial line.

11. The computer system as recited in claim 10, wherein the serial transfer unit comprises:

a timing generator, which generates a synchronous reference clock;

a serializer, which transforms parallel input data into serial format;

a transmit clock generator, which generates a timing signal used by the serializer;

a deserializer, which transforms serial input data into parallel format;

a receive clock generator, which generates a timing signal used by the deserializer;

a receive buffer, which couples the input of the deserializer to the differential serial line; and

a transmit buffer, which couples the output of the serializer and deserializer to the differential serial line.

12. The computer system as recited in claim 1, wherein first and second CPUs, cluster caches, and cluster cache controllers are all contained upon a monolithic substrate, comprising a CMOS integrated circuit.

13. A computer system, comprising:

a first cluster cache, operably coupled to a first central processing unit (CPU) and to a first memory subsystem via a first system bus, and coupled, through a path not including the first system bus, to a first I/O subsystem by a first port;

a second cluster cache, operably coupled to a second central processing unit (CPU) and to a second memory subsystem via a second system bus, and coupled, through a path not including the second system bus, to a second I/O subsystem by a second port; and

a differential serial line, adapted to transfer data between the first and second cluster caches.

14. The computer system as recited in claim 13, wherein the memory subsystem comprises a local cache.

15. A method for coordinating shared access to cache memory resources by first and second CPUs, comprising:

coupling a first cluster cache and a first local cache to a first central processing unit (CPU) via a first system bus;

coupling the first cluster cache and first local cache to a differential serial line, through a path not including the first system bus;

coupling a second cluster cache and a second local cache to a second central processing unit (CPU) via a second system bus;

coupling the second cluster cache and second local cache to the differential serial line, through a path not including the second system bus; and

transferring data between the first and second cluster caches via a differential serial line.

16. The method as recited in claim 15, further comprising transferring data between the first and second local caches via a differential serial line, without utilizing the first or second system bus.