Video parser

• US 6,330,665 B1
• Filed: 12/10/1997
• Issued: 12/11/2001
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Robbins, William P, Finch, Helen R, Wise, Adrian P., Boyd, Kevin J.
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US08/992,859
• Time in Patent Office: 1,462 Days
• Field of Search: 712/300, 712/220
• US Class Current: 712/300
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. A system for decoding video data, comprising:

a Huffman decoder;

an index to data (ITOD) unit, having a first mode of operation wherein an index number obtained from said Huffman decoder is converted into decoded data, and a second mode of operation wherein tokens received from said Huffman decoder are ignored, said tokens comprising a plurality of words, each said word including an extension indicator which indicates a presence or an absence of additional words in said token, a length of said token being determined by said extension indicators, whereby the length of said token can be unlimited;

an arithmetic logic unit (ALU); and

a data buffering means, whereby time spread for video pictures of varying data size can be controlled.

2. The system according to claim 1, further comprising:

an input shifter for decoding tokens and moving data into said Huffman decoder, wherein said data comprises tokens and non-token serial data; and

an interface interconnecting said Huffman decoder with said input shifter, said interface enabling serial processing for data and parallel processing for control;

wherein said interface comprises;

a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.

3. The system according to claim 2, wherein said interface further comprises:

a first valid wire for communicating a signal indicative of a token transfer from said sender to said receiver, and a second valid wire for communicating a signal indicative of a transfer of non-token serial data from said sender to said receiver.

4. The system according to claim 2, further comprising:

a token formatter for formatting tokens, whereby DATA tokens are created.

5. A system as recited in claim 2, wherein said interface further comprises:

electrical validation circuitry in at least one of said sender and said receiver to generate a validation signal for a first state when data stored in said stage is valid and for a second state when data stored in said stage is invalid, said validation circuitry including at least one storage device to store said validation signal;

an acceptance signal connected between said sender and said receiver conveying an acceptance signal indicative of the ability of said receiver to load data stored in the sender; and

enabling circuitry connected to said storage device for generating an enabling signal to enable loading of data and validation signals into said storage device;

wherein;

said storage device includes a primary data storage device and a secondary data storage device;

said data is loaded into said respective primary data storage devices and said validation signal is loaded into a respective secondary validation storage device at the same time;

data is loaded into said respective primary data storage device when said acceptance signal assumes an enabling state; and

said acceptance signal assumes said enabling state only when the acceptance signal associated with the data storage device of said receiver is in said enabling state or said data in said data storage device of said receiver is invalid.

6. The system according to claim 1, further comprising:

a state machine operatively associated with said Huffman decoder for controlling said Huffman decoder and generating command signals, wherein the command signals are communicated to said index to data unit and said arithmetic logic unit for control thereof; and

a ROM accessible to said state machine having separate stored programs for each of a plurality of picture standards, said programs being selectable by a token,

whereby processing for a plurality of picture standards is facilitated.

7. The system according to claim 6, wherein said extension indicator is an extension bit.

8. The system according to claim 6, further comprising a token formatter for formatting tokens, whereby DATA tokens are created.

9. The system according to claim 1, further comprising a token formatter for formatting tokens, whereby DATA tokens are created.

10. The system according to claim 1, wherein said extension indicator is an extension bit.

11. The system according to claim 1, wherein said first mode of operation and said second mode of operation are enabled in response to commands received from said Huffman decoder.