Method and apparatus for testing memory devices and displaying results of such tests

• US 6,330,693 B1
• Filed: 09/20/2000
• Issued: 12/11/2001
• Est. Priority Date: 12/04/1995
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lindsay, Brent
• Primary Examiner(s): Trammell, James P.
• Assistant Examiner(s): ELISCA, PIERRE E
• Application Number:
  US09/665,488
• Time in Patent Office: 447 Days
• Field of Search: 714/42, 714/48, 714/57, 714/53, 714/46, 714/54, 714/423, 365/200, 365/201
• US Class Current: 714/42
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

An apparatus and method for testing a semiconductor device allows error data to be displayed, in real time, based on the physical locations of the errors on the semiconductor device. A mapping circuit includes a router circuit, an error catch memory, and a topological circuit. The router circuit converts logical addresses employed by the semiconductor device to physical addresses employed by the error catch memory so that error data is appropriately routed from locations in the semiconductor device to corresponding locations in the error catch memory. The topological circuit then converts the physical addresses of the error data in the error catch memory to spatial addresses for allowing a host computer to rapidly display such errors as a bit map display on a visual display device. The router and topological circuits are preferably field programmable gate arrays or programmable read only memories so that the host computer can reprogram them for different semiconductor devices to be tested.

Claims

1. A method for testing memory locations in a memory array of a memory device, comprising:

testing a first memory location in the memory array;

writing test results for the first memory location to a location in a test memory corresponding to a physical address;

mapping a spatial address of a display memory to the physical address;

reading the test results from the location corresponding to the physical address and storing the test results in a location in a display memory corresponding to the spatial address; and

testing a second memory location in the memory array.

2. The method of claim 1, further comprising reading the test results from the display memory and displaying the test results at a location on a display corresponding to the spatial address.

3. The method of claim 1 wherein the first memory location corresponds to a first logical address and further comprises mapping the first logical address to a physical address in the test memory and writing the test results to the location in the a test memory corresponding to the physical address.

4. The method of claim 1 wherein mapping the spatial address to the physical address comprises referencing a look up table using the spatial address, the look up table storing the spatial address and having the physical address associated therewith.

5. The method of claim 1 wherein mapping the spatial address to the physical address comprises applying the spatial address to logic gates having outputs at which the physical address is provided.

6. A method for testing memory locations in a memory array of a memory device, comprising:

testing a memory location in the memory array corresponding to a logical address;

mapping the logical address of the memory location to a physical address;

storing test results for the tested memory location at a location in a test memory corresponding to the physical address; and

testing another memory location in the memory array.

7. The method of claim 6, further comprising:

mapping a spatial address of a display memory to the physical address corresponding to the location in the test memory at which the test results are stored; and

reading the test results from the location in the test memory and storing the test results in a location in the display memory corresponding to the spatial address.

8. The method of claim 7, further comprising reading the test results from the display memory and displaying the test results at a location on a display corresponding to the spatial address.

9. The method of claim 6, further comprising:

mapping a spatial address of a display memory to the physical address corresponding to the location in the test memory at which the test results are stored;

reading the test results from the location in the test memory and storing the test results in a location in the display memory corresponding to the spatial address; and

reading the test results from the display memory and displaying the test results at a location on a display corresponding to the spatial address,

wherein the process of mapping the spatial address, reading from test memory, storing in the display memory, reading from the display memory and displaying the test results are sequentially performed for each spatial address before repeating for a next spatial address.

10. The method of claim 6 wherein mapping the logical address to the physical address comprises referencing a look up table using the logical address, the look up table storing the logical address and having the physical address associated therewith.

11. The method of claim 6 wherein mapping the logical address to the physical address comprises applying the logical address to logic gates having outputs at which the physical address is provided.

12. A method for testing memory locations in a memory array, comprising:

producing test results for a memory location corresponding to an address defined in a logical address space;

mapping the address of the tested memory location into a physical address space;

storing the test results for the tested memory location at a test memory location corresponding to the physical address space; and

producing test results for a next memory location.

13. The method of claim 12, further comprising:

mapping an address defined in a spatial address space to an address defined in the physical address space;

reading the test results stored at the corresponding address in the physical address space;

storing the test result in a location in a display memory corresponding to the address defined in the spatial address space.

14. The method of claim 13, further comprising reading the test results from the display memory and displaying the test results at a location on a display corresponding to the spatial address.

15. A method for testing a memory device having a plurality of memory locations addressable by logical address, the method comprising the steps of:

loading a routing routine, based on a layout of memory locations in the memory device, which converts logical addresses of the memory device to physical addresses of an error memory;

applying a test pattern to the memory device; and

substantially simultaneously with applying the test pattern, determining error data from the memory device and routing it to the error memory according to the routing routine.

16. The method of claim 15, further comprising:

loading a mapping routine based upon the layout of a plurality of memory cells within the error memory into a topological circuit for converting spatial address to physical addresses; and

substantially simultaneously with applying the test pattern, constantly reading the error data from the error memory and displaying the error data at spatial locations on a display device based upon the mapping routine.

17. The method of claim 15 wherein loading the routing routine comprises loading a routine into a field programmable gate array.

18. The method of claim 15 wherein loading the routing routine comprises loading a routine into a read only memory that stores a look-up table for converting the logical addresses to physical addresses.

19. A method of testing a semiconductor device and outputting locations of errors in the semiconductor device, the semiconductor device having a plurality of locations addressable by logical address signals, the method comprising the steps of:

programming a converter for converting spatial addresses to physical addresses based on a layout of a plurality of memory locations in an error memory;

applying test signals to the semiconductor device, determining error data from the semiconductor device and routing the error data to the error memory; and

reading the error data from the error memory and visually outputting the error data at spatial locations based on the programmed converter.

20. The method of claim 19, further comprising:

programming a router for converting the logical addresses of the semiconductor device to physical addresses based on a layout of the locations in the semiconductor device; and

routing the error data to the error memory based on the programmed router.

21. The method of claim 19 wherein programming the converter comprises loading a routine into a field programmable gate array.

22. The method of claim 19 wherein programming the converter comprises loading a routine into a read only memory that stores a look-up table for converting the spatial addresses to physical addresses.

23. A test circuit for identifying errors in a memory device having a plurality of memory locations addressable by logical addresses, the test circuit comprising:

an error memory addressable by physical addresses for storing error data corresponding to a comparison between data applied to the plurality of memory locations in the memory device and data read from the plurality of memory locations; and

a mapping circuit coupled to the error memory and the memory device, the mapping circuit mapping the logical addresses of the memory device to physical addresses in the error memory at which the error data from the plurality of memory locations in the memory device are to be stored.

24. The test circuit of claim 23, further comprising a display memory and an address translation circuit coupled to the error memory, the translation circuit adapted to receive spatial addresses corresponding to locations in a display memory and to translate the spatial addresses to physical addresses from which error data are read, the error memory providing error data from a physical address to the corresponding spatial address in the display memory for storage therein.

25. The test circuit of claim 24, further comprising a display coupled to the display memory to display the error data in accordance with the spatial addresses.

26. A testing system for testing a memory device addressable by logical addresses and displaying the locations of errors in the memory device on a display device, the system comprising:

an error memory for storing error data corresponding to a comparison between written and read data to and from the memory device, each memory cell of the catch memory being addressable by a physical address; and

a topological circuit coupled to the error memory and adapted to receive spatial addresses, converting the spatial addresses to selected physical addresses, and providing error data corresponding to the selected physical addresses in response to the spatial addresses to allow the error data from the memory device to map to spatial addresses on the display device to display the locations of errors in the memory device.

27. The testing system of claim 26, further comprising a programmable router circuit coupled to the error memory to convert the logical addresses to physical addresses, and to route for storage the error data from locations corresponding to the logical addresses within the memory device to memory locations in the error memory corresponding to the physical addresses.

28. The testing system of claim 26 wherein the topological circuit comprises a field programmable gate array.

29. The testing system of claim 26 wherein the topological circuit comprises a read only memory to store a look-up table for converting the spatial addresses to physical addresses.