Method for manufacturing integrated devices including electromechanical microstructures, without residual stress

• US 6,331,444 B1
• Filed: 02/08/2000
• Issued: 12/18/2001
• Est. Priority Date: 02/09/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Montanini, Pietro, Ferrari, Paolo, Vigna, Benedetto, Ferrera, Marco, Castoldi, Laura
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/499,919
• Time in Patent Office: 679 Days
• Field of Search: 438/24, 438/48, 438/50, 438/52, 438/54, 438/55, 438/200, 438/432, 438/734
• US Class Current: 438/52
• CPC Class Codes: B81B 2203/033 Trenches
• CPC Class Codes: B81B 3/0072 For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers
• CPC Class Codes: B81C 1/00666 Treatments for controlling internal stress or strain in MEMS structures
• CPC Class Codes: B81C 2201/017 Methods for controlling internal stress of deposited layers not provided for in B81C2201/0164 - B81C2201/0169
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 2015/0828 the mass being of the paddle type being suspended at one of its longitudinal ends

Abstract

On a substrate of semiconductor material, a sacrificial region is formed and an epitaxial layer is grown; a stress release trench is formed, surrounding an area of the epitaxial layer, where an integrated electromechanical microstructure is to be formed; the wafer is then heat treated, to release residual stress. Subsequently, the stress release trench is filled with a sealing region of dielectric material, and integrated components are formed. Finally, inside the area surrounded by the sealing region, a microstructure definition trench is formed, and the sacrificial region is removed, thus obtaining an integrated microstructure with zero residual stress.

Claims

1. A method for manufacturing integrated devices including electromechanical microstructures, comprising the steps of forming a wafer of semiconductor material, including a substrate and an operative layer;

forming an electromechanical microstructure in an area of said operative layer, and wherein before said step of forming a microstructure, the steps are carried out of forming a stress release trench, surrounding said area in said operative layer, and carrying out an annealing of said area including the stress release trench to release stress in the area.

2. The method of claim 1 wherein said stress release trench extends throughout the depth of said operative layer.

3. The method of claim 1 wherein after said step of heat treatment, the step is carried out of filling said stress release trench with sealing material.

4. The method of claim 3 wherein said sealing material is a dielectric material.

5. The method of claim 3 or 4 wherein said sealing material is BPSG.

6. The method of claim 1 wherein said operative layer is an epitaxial layer.

7. The method of claim 6 wherein said step of forming a wafer comprises the steps of:

forming a sacrificial region on said substrate; and

growing a pseudoepitaxial layer, said pseudoepitaxial layer comprising at least one monocrystalline region above said substrate, and one polycrystalline region above said sacrificial region; and

after the step of heat treatment and before said step of forming a microstructure, the step is carried out of forming electronic components in said monocrystalline region of said pseudoepitaxial layer;

and said step of forming a microstructure comprises the steps of excavating a structure definition trench inside said polycrystalline region, and removing said sacrificial region.

8. The method of claim 1 wherein said step of forming a wafer comprises the steps of depositing said operative layer on said substrate.

9. The method of claim 8 wherein said operative layer is a semiconductor material layer having a polycrystalline structure.

10. A method for manufacturing integrated devices including electromechanical microstructures, comprising:

forming a wafer of semiconductor material, including a substrate and an epitaxial layer, comprising;

forming a sacrificial region on the substrate;

growing a pseudoepitaxial layer, the pseudoepitaxial layer comprising at least one monocrystalline region above the substrate and one polycrystalline region above the sacrificial region;

forming a stress release trench surrounding an area in the epitaxial layer and carrying out heat treatment of the area;

forming electronic components in the monocrystalline region of the pseudoepitaxial layer; and

forming an electromechanical microstructure in the area of the epitaxial layer, comprising excavating a structure definition trench inside the polycrystalline region and removing the sacrificial region.