Insulated gate semiconductor device and manufacturing method thereof

• US 6,331,466 B1
• Filed: 05/02/2000
• Issued: 12/18/2001
• Est. Priority Date: 02/21/1994
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki, Minato, Tadaharu, Harada, Masana, Nishihara, Hidenori
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thao P.
• Application Number:
  US09/563,206
• Time in Patent Office: 595 Days
• Field of Search: 438/253, 438/268, 438/315, 438/624, 438/270, 438/275, 257/678, 257/213, 257/203
• US Class Current: 438/268
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N⁺ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N⁺ emitter layer (206). Furthermore, the ladder-like N⁺ emitter layer (206) is formed adjacent to the trench (207), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.

Claims

1. A method of manufacturing an insulated gate type semiconductor device in which a plurality of insulated gate type semiconductor elements having trench gate are arranged substantially in a stripe form in a semiconductor base body, comprising the steps of:

(a) preparing the semiconductor base body defining an upper main surface and a lower main surface and having a first semiconductor layer of a first conductivity type exposed on the upper main surface;

(b) forming a second semiconductor layer of a second conductivity type exposed the upper main surface of said semiconductor base body in an upper surface portion of said first semiconductor layer by introducing impurity of the second conductivity type in the upper main surface of said semiconductor base body;

(c) selectively introducing impurity of the first conductivity type in the upper main surface of said semiconductor base body to selectively form a third semiconductor layer of the first conductivity type exposed on the upper main surface in a lattice-like form in an upper surface portion of said second semiconductor layer;

(d) selectively carrying out etching from the upper main surface of said semiconductor base body to form a trench which opens in said upper main surface, reaches said first semiconductor layer, and includes at least as a part thereof a plurality of trenches arranged substantially in a stripe form, each of said plurality of trenches opens along and inside a portion of the lattice-like exposed surface of said third semiconductor layer extending in a stripe form;

(e) forming a first insulating film covering an inner wall of said trench and the upper main surface of said semiconductor base body;

(f) burying a gate electrode in said trench covered with said first insulating film;

(g) forming a second insulating film on said first insulating film and said gate electrode;

(h) selectively applying etching to said second insulating film to selectively remove said second insulating film substantially in a zonal form interposed between adjacent said strip-like trenches, separated from the trenches and extending along the trenches;

(i) forming a first conductor to cover said second insulating film and a portion from where it is removed; and

(j) forming a second conductor on the lower main surface of said semiconductor base body.

2. A method of manufacturing an insulated gate type semiconductor device comprising the steps of:

(a) preparing a semiconductor base body defining an upper main surface and a lower main surface and having a first semiconductor layer of a first conductivity type exposed on the upper main surface;

(b) forming a second semiconductor layer of a second conductivity type exposed on the upper main surface of said semiconductor base body in an upper surface portion of said first semiconductor layer by introducing impurity of the second conductivity type in the upper main surface of said semiconductor base body;

(c) selectively introducing impurity of the first conductivity type in the upper main surface of said semiconductor base body to selectively form a third semiconductor layer of the first conductivity type selectively exposed on the upper main surface in the upper surface portion of said second semiconductor layer;

(d) selectively applying etching from the upper main surface of said semiconductor base body to form a trench reaching said first semiconductor layer;

(e) forming a first insulating film covering an inner wall of said trench and the upper main surface of said semiconductor base body;

(f) burying a gate electrode in said trench covered with said first insulating film;

(g) forming a second insulating film on said first insulating film and said gate electrode;

(h) selectively applying etching to said second insulating film to selectively remove said second insulating film in a form separated from said trench and along said trench;

(i) selectively introducing element containing platinum into the upper main surface of said semiconductor base body using said second insulating film as a shield to selectively form a conductive layer having platinum silicide on the upper main surface potion of said semiconductor base body;

(j) forming a first conductor to cover said second insulating film the a portion from where it is removed; and

(k) forming a second conductor on the lower main surface of said semiconductor base body.

6. The method of manufacturing a semiconductor device according to claim 2, wherein

said step (f) comprises the steps of

(f-1) selectively forming a shield over said upper main surface; and

(f-2) selectively implanting the impurity of the first conductivity type in said upper main surface by using said shield and thereafter diffusing it to form said seventh semiconductor layer and form an eighth semiconductor layer of the first conductivity type having an impurity concentration higher than that of said third semiconductor layer in a region inside edges of said third semiconductor layer in said upper main surface to be exposed to said first region and not to be exposed to said second region.

3. A method of manufacturing an insulated gate type semiconductor device, comprising the steps of:

(a) preparing a semiconductor base body defining an upper main surface and a lower main surface and having a first semiconductor layer of a first conductivity type exposed on the upper main surface;

(b) forming, on an upper surface portion of said first semiconductor layer, a second semiconductor layer of a second conductivity type exposed on the upper main surface of said semiconductor base body by introducing impurity of the second conductivity type in the upper main surface of said semiconductor base body;

(c) selectively introducing impurity of the first conductivity type in the upper main surface of said semiconductor base body to selectively form a third semiconductor layer of the first conductivity type selectively exposed on the upper main surface in the upper surface portion of said second semiconductor layer;

(d) selectively applying etching from the upper main surface of said semiconductor base body to form a trench reaching said first semiconductor layer;

(e) forming a first insulating film covering an inner wall of said trench and the upper main surface of said semiconductor base body;

(f) providing a polysilicon layer so as to fill said trench covered with said first insulating film and so as to have a predetermined or larger thickness above the upper main surface of said semiconductor base body covered with said first insulating film;

(g) applying etching to the upper surface of said polysilicon layer to adjust the thickness from the upper main surface of said semiconductor base body to a predetermined magnitude;

(h) selectively applying etching to said polysilicon layer to remove the polysilicon layer except a portion buried in said trench which functions as a gate electrode and a portion which functions as a gate interconnection;

(i) forming a second insulating film on said first insulating film and said gate electrode;

(j) selectively applying etching to said second insulating film to selectively remove said second insulating film in a form separated from said trench and along said trench;

(k) forming a first conductor to cover said second insulating film and a portion from where it is removed; and

(l) forming a second conductor on the lower main surface of said semiconductor base body.

5. A method of manufacturing a semiconductor device according to claim 3, wherein

the impurity of the first conductivity type is selectively implanted in said upper main surface with said first gate electrode and said second gate electrode used as shields and thereafter diffused to form said third semiconductor layer and said fifth semiconductor layer and selectively form an eighth semiconductor layer of the first conductivity type at the same time in said upper surface to be shallower than said second semiconductor layer and away from both said third semiconductor layer and said fifth semiconductor layer in said steps (b) and (c).

4. A method of manufacturing an insulated gate type semiconductor device, comprising the steps of:

(a) preparing a semiconductor base body defining an upper main surface and a lower main surface and having a first semiconductor layer of a first conductivity type exposed on the upper main surface;

(b) forming, on an upper surface portion of said first semiconductor layer, a second semiconductor layer of a second conductivity type exposed on the upper main surface of said semiconductor base body by introducing impurity of the second conductivity type in the upper main surface of said semiconductor base body;

(c) selectively introducing impurity of the first conductivity type in the upper main surface of said semiconductor base body to selectively form a third semiconductor layer of the first conductivity type selectively exposed on the upper main surface in an upper surface portion of said second semiconductor layer;

(d) selectively applying etching from the upper main surface of said semiconductor base body to form a trench reaching said first semiconductor layer;

(e) forming a first insulating film covering an inner wall of said trench and the upper main surface of said semiconductor base body;

(f) providing a polysilicon layer so as to fill said trench covered with said first insulating film and so as to have a predetermined thickness above the upper main surface of said semiconductor base body covered with said first insulating film;

(g) selectively applying etching to said polysilicon layer to remove said polysilicon layer except a portion buried in said trench which functions as a gate electrode and a portion which functions as a gate interconnection;

(h) forming a second insulating film on said first insulating film and said gate electrode;

(i) selectively applying, etching to said second insulating film to selectively remove said second insulating film in a form separated from said trench and along said trench;

(j) forming a first conductor to cover said second insulating film and a portion from where it is removed; and

(k) forming a second conductor on the lower main surface of said semiconductor base body.