Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers

• US 6,331,468 B1
• Filed: 05/11/1998
• Issued: 12/18/2001
• Est. Priority Date: 05/11/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Kapre, Ravindra A., Puchner, Helmut, Aronowitz, Sheldon, Kimball, James P.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MAI, ANH D
• Application Number:
  US09/076,399
• Time in Patent Office: 1,317 Days
• Field of Search: 438/301, 438/303, 438/305, 438/306, 438/265, 438/290, 438/216, 438/287, 438/591, 438/595, 438/653, 438/776, 438/786, 257/411, 257/410
• US Class Current: 438/287
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode. This amorphous layer is then implanted with a dopant capable of forming a source/drain region in the underlying silicon substrate by subsequent diffusion of the implanted dopant from the amorphous silicon layer into the substrate. The structure is then annealed to diffuse the dopant from the implanted silicon layer into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to dope the polysilicon. The annealing further serves to cause the amorphous silicon layer to crystalize to polycrystalline silicon (polysilicon). In one embodiment, the polysilicon layer is then nitridized to convert it to a silicon nitride layer which is then patterned to form silicon nitride spacers on the sidewalls of the polysilicon gate electrode to electrically insulate the gate electrode from the source/drain regions. The process may be further modified to also create LDD or HDD source/drain regions in the substrate (depending on the concentration of the dopant), using multiple implants into the same silicon layer or by the sequential use of several silicon layers, each of which is used as an implantation and out-diffusion layer.

Claims

1. A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

a) forming a gate oxide layer over a single crystal semiconductor substrate;

b) forming a dopant-implant barrier layer containing nitrogen and silicon over said single crystal semiconductor substrate;

c) forming a polysilicon gate electrode over said barrier layer;

d) removing exposed portions of said barrier layer remaining after formation of said gate electrode thereon;

e) forming an amorphous silicon layer over said integrated circuit structure;

f) implanting said amorphous silicon layer with a first dopant capable of forming source/drain regions in the underlying semiconductor substrate;

g) annealing said amorphous silicon layer;

1) to crystallize said amorphous silicon layer to form a polysilicon layer;

2) to diffuse said implanted dopant from said silicon layer into said substrate to form said source/drain regions in said substrate; and

3) to diffuse said dopant into said polysilicon gate electrode;

h) then nitridating said polysilicon layer to convert said polysilicon layer into a silicon nitride layer; and

i) then anisotropically etching said silicon nitride layer to form silicon nitride spacers on the sidewalls of said polysilicon gate electrode to electrically insulate said gate electrode from said source/drain regions in said substrate.

2. The process of claim 1 wherein said step of implanting said amorphous silicon layer with said first dopant further comprises implanting said amorphous silicon layer with a dopant selected from the group consisting of boron, phosphorus, and arsenic.

3. The process of claim 1 including the further steps of:

a) forming a further amorphous silicon layer over said integrated circuit structure after said step of forming said first silicon nitride spacers;

b) implanting said further amorphous silicon layer with a second dopant at a total dopant concentration higher than said first dopant and sufficient to form source/drain regions in said substrate upon subsequent annealing of said structure to diffuse said second dopant into said substrate;

c) annealing said structure to diffuse said second implanted dopant into said substrate to form said source/drain regions in said substrate and to convert said further amorphous silicon layer into a further polysilicon layer;

d) nitridating said further polysilicon layer to form a second layer of silicon nitride; and

e) then anisotropically etching said second silicon nitride layer to form second silicon nitride spacers adjacent said first silicon nitride spacers on the sidewalls of said polysilicon gate electrode;

whereby said first dopant creates less heavily doped regions in said substrate between said source/drain regions and a channel region in said substrate beneath said polysilicon gate electrode.

4. The process of claim 3 wherein said first dopant and said second dopant comprise the same dopant material.

5. A The process of claim 1 including the further step of implanting said amorphous silicon layer with a second dopant after said step of implanting said amorphous silicon layer with said first dopant.

6. The process of claim 1 wherein said nitridating step further comprises exposing said polysilicon layer to a nitrogen plasma to convert said polysilicon layer into a silicon nitride layer.

7. The process of claim 1 wherein said step of forming said barrier layer further comprises nitridating said gate oxide layer, using a nitrogen plasma to form a barrier layer comprising a silicon, oxygen, and nitrogen compound.

8. The process of claim 1 wherein said step of forming said barrier layer further comprises the steps of:

a) forming a silicon layer over said previously formed gate oxide layer; and

b) nitridating said silicon layer, using a nitrogen plasma to form said barrier layer comprising a silicon and nitrogen compound.

9. A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

a) forming a dopant-implant barrier layer containing nitrogen and silicon over a single crystal semiconductor substrate;

b) forming a polysilicon gate electrode over said barrier layer;

c) removing exposed portions of said barrier layer;

d) forming a first amorphous silicon layer over said barrier layer and said polysilicon gate electrode;

e) implanting said first amorphous silicon layer with a first dopant capable of forming doped regions in the underlying semiconductor substrate which are less heavily doped than source/drain regions subsequently formed in said substrate;

f) annealing said first amorphous silicon layer;

i) to form a first polysilicon layer;

ii) to diffuse said implanted first dopant from said first silicon layer through said barrier layer into said substrate to form said doped regions in said substrate; and

iii) to diffuse said implanted first dopant into said polysilicon gate electrode;

g) then nitridating said first polysilicon layer, using a nitrogen plasma to convert said first polysilicon layer into a first silicon nitride layer;

h) then anisotropically etching said first silicon nitride layer to form first silicon nitride spacers on the sidewalls of said polysilicon gate electrode;

i) forming a second layer of amorphous silicon over said structure;

j) implanting said second amorphous silicon layer with a second dopant capable of forming source/drain regions in the underlying semiconductor substrate;

k) annealing said second amorphous silicon layer;

i) to form a second polysilicon layer; and

ii) to diffuse said implanted second dopant from said second silicon layer through said barrier layer into said substrate to form said source/drain regions in said substrate;

l) then nitridating said second polysilicon layer, using a nitrogen plasma to convert said second polysilicon layer into a second silicon nitride layer; and

m) then anisotropically etching said second silicon nitride layer to form second silicon nitride spacers adjacent said first silicon nitride spacers on the sidewalls of said polysilicon gate electrode;

whereby source/drain regions are formed in said substrate separated from a channel region in said substrate beneath said gate electrode by less heavily doped regions in said substrate.

10. The process of claim 9 wherein said step of forming said barrier layer further comprises:

a) forming a gate oxide layer over said single crystal semiconductor substrate; and

b) nitridating said gate oxide layer, using a nitrogen plasma to form a barrier layer comprising a silicon, oxygen, and nitrogen compound.

11. The process of claim 9 wherein said step of forming said barrier layer further comprises the steps of:

a) forming a gate oxide layer over said single crystal semiconductor substrate;

b) forming a silicon layer over said gate oxide layer; and

c) nitridating said silicon layer, using a nitrogen plasma to form a barrier layer comprising a silicon and nitrogen compound over said gate oxide layer.

12. A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

a) forming a dopant-implant barrier layer containing nitrogen and silicon over a first area of a single crystal semiconductor substrate;

b) forming a polysilicon gate electrode over a central portion of said barrier layer of smaller area than said first area;

c) forming an amorphous silicon layer over said substrate, including said polysilicon gate electrode and exposed portions of said barrier layer;

d) implanting said amorphous silicon layer with a first dopant at a first concentration capable of forming source/drain regions in the underlying single crystal semiconductor substrate;

e) implanting said amorphous silicon layer with a second dopant having a faster diffusion rate than said first dopant, but at a second concentration smaller than said first concentration, and capable of forming doped regions in said substrate less heavily doped than said source/drain regions;

f) annealing said amorphous silicon layer;

i) to form a polysilicon layer;

ii) to diffuse said implanted first and second dopants from said silicon layer into said substrate to form said source/drain regions and said less heavily doped regions in said substrate; and

iii) to diffuse said dopants into said polysilicon gate electrode;

whereby said faster diffusing second dopant will laterally diffuse toward a channel region in said substrate beneath said polysilicon gate electrode at a faster rate than said first dopant to thereby form said less heavily doped regions between said channel region and said source/drain regions;

g) then nitridating said polysilicon layer, using a nitrogen plasma to convert said polysilicon layer into a silicon nitride layer; and

h) then anisotropically etching said silicon nitride layer to form silicon nitride spacers on the sidewalls of said polysilicon gate electrode to electrically insulate said gate electrode from said source/drain regions in said substrate.

13. The process of claim 12 wherein said step of forming said barrier layer further comprises:

a) forming a gate oxide layer over said single crystal semiconductor substrate; and

b) nitridating said gate oxide layer, using a nitrogen plasma to form a barrier layer comprising a silicon, oxygen, and nitrogen compound.

14. The process of claim 12 wherein one of said first and second dopants comprises arsenic and the other of said first and second dopants comprises phosphorus.

15. The process of claim 14 wherein said arsenic dopant is implanted into said amorphous silicon layer at a higher total dopant concentration than said phosphorus dopant.

16. A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

a) forming a gate oxide layer over a single crystal semiconductor substrate;

b) forming a silicon layer over said gate oxide layer;

c) nitridating said silicon layer to form a dopant-implant barrier layer comprising a silicon and nitrogen compound over said gate oxide layer;

d) forming a polysilicon gate electrode over said barrier layer;

e) removing all of said barrier layer not under said polysilicon gate electrode;

f) forming an amorphous silicon layer over exposed portions of said integrated circuit structure;

g) implanting said amorphous silicon layer with a first dopant capable of forming doped regions in the underlying semiconductor substrate;

h) annealing said amorphous silicon layer;

1) to crystallize said amorphous silicon layer into a polysilicon layer;

2) to diffuse said implanted first dopant from said silicon layer into said substrate to form said doped regions in said substrate; and

3) to diffuse said first dopant into said polysilicon gate electrode;

i) then nitridating said polysilicon layer to convert said polysilicon layer into a first silicon nitride layer; and

j) then anisotropically etching said silicon nitride layer to form first silicon nitride spacers on the sidewalls of said polysilicon gate electrode to electrically insulate said gate electrode from said doped regions in said substrate.

17. The process of claim 16 including the further step of removing all of said gate oxide layer exposed by said step of removing all of said barrier layer not under said polysilicon gate electrode.

18. A process for forming an integrated circuit structure on a semiconductor substrate which comprises:

a) forming a gate oxide layer of silicon oxide over a single crystal semiconductor substrate;

b) nitridating said gate oxide layer to form a dopant-implant barrier layer comprising silicon, oxygen, and nitrogen over said single crystal semiconductor substrate;

c) forming a polysilicon gate electrode over said barrier layer;

d) removing all of said barrier layer not under said polysilicon gate electrode;

e) forming an amorphous silicon layer over exposed portions of said integrated circuit structure;

f) implanting said amorphous silicon layer with a first dopant capable of forming doped regions in the underlying semiconductor substrate;

g) annealing said amorphous silicon layer;

1) to crystallize said amorphous silicon layer into a polysilicon layer;

2) to diffuse said implanted first dopant from said silicon layer into said substrate to form said doped regions in said substrate; and

3) to diffuse said first dopant into said polysilicon gate electrode;

h) then nitridating said polysilicon layer to convert said polysilicon layer into a first silicon nitride layer; and

i) then anisotropically etching said silicon nitride layer to form first silicon nitride spacers on the sidewalls of said polysilicon gate electrode to electrically insulate said gate electrode from said doped regions in said substrate.