Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material

• US 6,331,480 B1
• Filed: 02/18/1999
• Issued: 12/18/2001
• Est. Priority Date: 02/18/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tao, Hun-Jan, Tsai, Chia-Shiung, Cheng, Yao-Yi
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Peralta, Ginette
• Application Number:
  US09/252,469
• Time in Patent Office: 1,034 Days
• Field of Search: 438/622, 438/624, 438/637
• US Class Current: 438/624
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

A method for improving the adhesion, between an overlying insulator layer, and an underlying low K layer, used for forming a composite layer, damascene mask pattern, wherein the damascene mask pattern is used as an interlevel dielectric layer, between metal interconnect structures, has been developed. A treatment, comprised of aqueous NH₄OH solutions, or of UV curing procedures, is performed on the top surface of the low K layer, prior to deposition of the overlying insulator layer. The treatment, resulting in a roughened top surface of the low K layer, allows removal of masking photoresist shapes, to be aggressively accomplished using wet strippers, without adhesion loss at the insulator—low K layer interface.

Claims

1. A method of fabricating a metal interconnect structure, on a semiconductor substrate, using a silicon oxide, damascene mask pattern, formed on underlying thick low K—

insulator, composite layer, and featuring a UV treatment performed on said thick low K layer, prior to deposition of the said silicon oxide layer, used for the damascene mask pattern, with said UV treatment used to improve the adhesion between said silicon oxide layer, and said thick low K layer, comprising the steps of;

forming said thick low K layer, and an underlying insulator layer, on an underlying, first metal interconnect structure;

forming a via hole in said thick low K layer, and in said underlying insulator layer, exposing a portion of the top surface, of said first metal interconnect structure;

forming a metal plug structure, in said via hole;

performing said treatment, comprised of UV exposure of the top surface of said thick low k layer, creating a roughened top surface for said thick low K layer;

depositing a second insulator layer, on said roughened top surface of said thick low K layer;

depositing a silicon oxide layer on said second insulator layer;

using a photoresist shape, with a first opening, as a mask, to form said silicon oxide, damascene mask pattern, via removal of regions of said silicon oxide layer, exposed in said first opening in said photoresist shape, and with a second opening, in said silicon oxide, damascene mask pattern, exposing a portion of the top surface of said second insulator layer;

removing said portion, of said second insulator layer, exposed in said second opening, in said silicon oxide, damascene mask pattern, exposing the top surface of said metal plug structure;

removing said photoresist shape, from the top surface of said silicon oxide, damascene mask pattern; and

forming a second metal interconnect structure, in said second opening, in said silicon oxide, damascene mask pattern.

2. The method of claim 1, wherein said thick low K layer, is chosen from a group that includes, FSG or HSQ, obtained via a PECVD procedure, for said FSG layer, and via a spin-on procedure, for said HSQ layer, both at a thickness between about 3000 to 5000 Angstroms, and both with a dielectric constant between about 2.5 to 3.5.

3. The method of claim 1, wherein said second insulator layer, is a silicon oxide, or a silicon nitride layer, obtained via PECVD procedures, at a thickness between about 500 to 1000 Angstroms.

4. The method of claim 1, wherein said silicon oxide layer is obtained via PECVD procedures, to a thickness between about 3000 to 5000 Angstroms.

5. The method of claim 1, wherein said silicon oxide, damascene mask pattern, is formed via an anisotropic RIE procedure, using CHF₃, or CF₄ as an etchant, and using said first opening, in said photoresist shape as a mask.

6. The method of claim 1, wherein said photoresist shape is removed via plasma oxygen ashing and via use of a wet stripper, such as an amine solution, performed at a temperature between about 100 to 115°

C.