Secure programmable logic device

• US 6,331,784 B1
• Filed: 07/28/2000
• Issued: 12/18/2001
• Est. Priority Date: 07/28/2000
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Kunnari, Nancy D., Kuo, Harry H., Mason, Martin T.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/627,351
• Time in Patent Office: 508 Days
• Field of Search: 326/41, 326/8, 326/40, 326/46, 326/47, 326/37, 713/200, 711/163
• US Class Current: 326/8
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17768 for security

Abstract

A programmable logic chip and configuration memory chip are mounted within a multi-chip module to form a single package. The configuration memory has a security bit which in a first state allows programming and read-back of configuration data in the memory chip via external pins of the package, and in a second state allows only erase command to be communicated to the memory chip via the external pins. The internal data transfer connection between the memory chip and programmable logic chip is enabled when the security bit is in the second state and the memory chip is in a read-back mode, allowing configuration data to be loaded into the logic chip upon power up.

Claims

1. A secure programmable logic integrated circuit system, comprising:

a multi-chip module having external pins;

a programmable logic chip mounted in said multi-chip module and in communication with said external pins; and

a configuration memory chip mounted in said multi-chip module, the configuration memory chip storing configuration data for programming a configuration of said programmable logic chip via a data transfer connection internal to said multi-chip module, the configuration memory in communication with said external pins for program and erase commands and configuration data to be stored in said configuration memory chip,

wherein said configuration memory chip includes a security bit, said security bit having a first state in which configuration data may be programmed and read-back through said external pins of said multi-chip module, said security bit having a second state in which only an erase command can be communicated via said external pins and in which said internal data transfer connection is enabled.

2. The system of claim 1 wherein said programmable logic chip comprises a field programmable gate array (FPGA).

3. The system of claim 2 wherein said programmable logic chip includes non-programmable logic block, integrated therein.

4. The system of claim 2 wherein said programmable logic chip also incorporates a microcontroller.