Customizable and programmable cell array

• US 6,331,790 B1
• Filed: 09/11/2000
• Issued: 12/18/2001
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi, Zeman, Richard, Cooke, Laurance, Wurman, Zeʼev
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/659,783
• Time in Patent Office: 463 Days
• Field of Search: 326/37-41
• US Class Current: 326/41
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

This invention discloses a customizable and programmable integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for customization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

Claims

1. A semiconductor device comprising:

a logic array including a multiplicity of identical logic cells, each identical logic cell comprising at least one look-up table, metal connection layers overlying the multiplicity of identical logic cells for providing at least one permanent customized direct interconnect between various inputs and outputs thereof.

2. A semiconductor device according to claim 1 and wherein each said logic cell comprises at least one multiplexer and said at least one look-up table provides an input to the at least one multiplexer.

3. A device according to claim 2 and also comprising at least one logic gate connected to at least one input of said look-up table.

4. A device according to claim 3 and wherein said at least one multiplexer is configured to perform a logic operation on said input from said at least one look-up tables.

5. A semiconductor device according to claim 1, wherein said at least one look-up table is programmable.

6. A semiconductor device according to claim 1 wherein said logic cell includes at least one simple logic gate selectably connected to at least one logic cell output.

7. A logic array according to claim 1 and also comprising a flip-flop.

8. A semiconductor device according to claim 5, further comprising:

a plurality of pins,

wherein said at least one look-up table is programmable by means of electrical signals supplied thereto via at least some of said plurality of pins.

9. A semiconductor device according to claim 1 wherein said Look-Up-Table is programmed at least twice during a testing process.

10. A semiconductor device according to claim 1, said semiconductor device being designed such that the functionality of said multiplicity of identical logic cells as being either logic or memory is determined by the configuration of said metal layers.

11. A semiconductor device according to claim 10 and wherein said semiconductor device is designed such that the functionality of said multiplicity of identical logic cells as being either logic or memory is determined solely by the configuration of said metal layers.

12. A semiconductor device according to claim 1, wherein said semiconductor device includes at least one ferroelectric element.

13. A semiconductor device according to claim 1, wherein said metal layers include at least three metal layers, and wherein said customized interconnection is determine by a single custom via layer.

14. A semiconductor device according to claim 2, and also comprising:

at least one switch arranged in series between at least one output of said at least one look up table and at least one input of said at least one multiplexer, said switch enabling one of at least two of the following inputs to be supplied to said at least one input of said at least one multiplexer;

logic zero, logic 1, and said at least one output of said at least one look up table.

15. A semiconductor device according to claim 14, and also comprising a flip flop receiving an output of said at least one multiplexer and wherein said at least one switch enables one of at least two of the following inputs to be supplied to said at least one input of said at least one multiplexer:

logic zero, logic 1, an output of said at least one look up table and an output of said flip flop.

16. A semiconductor device according to claim 1 and wherein at least a majority of said metal connection layers constitutes repeated subpatterns.

17. A semiconductor device according to claim 1 wherein said Look-Up-Table comprises a mask programmable memory cell.

18. A semiconductor device according to claim 1 wherein said Look-Up-Table comprises the following:

at least two inputs; and

an electronic circuit which provides high speed response to changes in one of said two inputs with respect to the response time of changes to the other input.

19. A semiconductor device according to claim 2, further comprising:

an inverter selectably connectable to at least one of an output of said at least one multiplexer and an output of said at least one look up table.

20. A semiconductor device comprising:

a logic array comprising a multiplicity of identical logic cells, each identical logic cell including at least one flip-flop; and

a metal connection layer overlying the multiplicity of identical logic cells for directly interconnecting various inputs and outputs thereof in a customized manner.

21. A semiconductor device according to claim 20 and also comprising a clock tree providing clock inputs to at least one of said at least one flip-flop of said multiplicity of identical logic cells.

22. A semiconductor device according to claim 20 and wherein each logic cell receives a scan signal input which determines whether the cell operates in a normal operation mode or a test operation mode, wherein in a test operation mode nearly each flip-flop receives an input from an adjacent flip-flop thereby to define a scan chain.

23. A semiconductor device according to claim 21 wherein said clock tree comprises a clock signal and an inverted clock signal.