Phase leg with depletion-mode device

• US 6,331,794 B1
• Filed: 03/09/2000
• Issued: 12/18/2001
• Est. Priority Date: 03/10/1999
• Status: Expired due to Term

• Current Assignee: Enphase Energy Incorporated
• Original Assignee: Richard A. Blanchard
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/521,487
• Time in Patent Office: 649 Days
• Field of Search: 327/108, 327/111, 327/112, 327/423, 327/424, 327/427, 326/86, 326/87, 326/117
• US Class Current: 327/112
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

A technique for supplying drive voltage to the gate of a high-side depletion-mode N-channel MOS-device for phase-leg circuits, H-bridges, or any circuit with a depletion-mode N-channel MOS-device with its source at a voltage above local ground.

Claims

1. A circuit comprising:

a first reference voltage connected to a first drive element;

a second reference voltage connected to a second drive element;

a third reference voltage having a polarity opposite that of the first reference voltage;

a switch having a first terminal connected to the third reference voltage and a second terminal connected to a gate of the first drive element;

the first and second drive elements connected to a load node to selectably pull said load node toward first and second reference voltages respectively, said load node having a third voltage;

said first drive element comprising a depletion-mode power device, which is in its “

off”

state whenever the third reference voltage is applied to the gate terminal via the switch.

2. The circuit of claim 1, wherein said first drive element is DMOS.

3. The circuit of claim 1, wherein said first drive element is an N-channel depletion-mode device.

4. The circuit of claim 1, wherein said first drive element and said second drive element are integrated on a single die.

5. The circuit of claim 1, wherein said first drive element and second drive element are fabricated simultaneously using substantially the same process steps.

6. The circuit of claim 1, wherein said first drive element and second drive element are incorporated in a single integrated circuit.

7. A circuit comprising:

a first reference voltage connected to a first drive element;

a second reference voltage connected to a second drive element;

the first and second drive elements being connected to a load node to selectable pull said load node toward first and second reference voltages respectively, said load node having a third voltage;

said first drive element being a depletion-mode device, and said second drive element comprises an enhancement-mode device and a resistor connected between a source terminal and a gate terminal of the enhancement-mode device.

8. The circuit of claim 7, wherein said first drive element is DMOS.

9. The circuit of claim 7, wherein said first and second drive elements are incorporated in a single integrated circuit.

10. The circuit of claim 7, wherein said first drive element is an N-channel depletion-mode device.

11. A circuit comprising:

first reference voltage connected to a first drive element;

second reference voltage connected to a second drive element;

the first and second drive elements connected to a load node to selectably pull said load node toward first and second reference voltages respectively, said load node having a third voltage;

said first and second drive elements having substantially identical diffusion structures;

said first drive element being a depletion-mode device, and said second drive element comprising an enhancement-mode device and a second depletion-mode device with a drain terminal connected to a gate terminal of the enhancement-mode device and a first source terminal connected to a source terminal of the enhancement-mode device.

12. The circuit of claim 11, wherein said first drive element and the enhancement-mode device have substantially identical doping concentrations and device geometries.

13. The circuit of claim 11, wherein said first and second drive elements comprise a phase-leg.

14. The circuit of claim 11, wherein said first and second drive elements are incorporated in a single integrated circuit.

15. The circuit of claim 11, wherein said first drive element is fully turned off only when a threshold voltage which is outside of the range of said first reference voltage and said third voltage is applied to the gate of said first drive element.

16. The circuit of claim 11, wherein said first drive element is DMOS.

17. A bridge circuit comprising:

a first phase leg, connected to selectably source current from a positive reference voltage to a load device; and

a second phase-leg, connected to selectably source current from said positive reference voltage to said load device;

said first phase leg comprising a high-side switch and a low-side switch wherein said high-side switch is an N-channel depletion-mode power device; and

said second phase leg comprising a high-side switch and a low-side switch, wherein said high-side switch is an N-channel depletion-mode power device.

18. The circuit of claim 17, wherein said N-channel depletion-mode power devices are DMOS.

19. The circuit of claim 17, wherein said high-side switches have gate drive voltages that are negative with respect to their sources.

20. The circuit of claim 17, wherein said first and second phase legs are incorporated in a single integrated circuit.

21. The circuit of claim 17, further comprising a microprocessor functionally connected to operate said high-side and low-side switches.