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Video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing

  • US 6,331,856 B1
  • Filed: 11/22/1995
  • Issued: 12/18/2001
  • Est. Priority Date: 11/22/1995
  • Status: Expired due to Term
First Claim
Patent Images

1. An interactive video game system comprising:

  • an interactive user input device;

    a main processor coupled to the input device, the main processor having an address space, the main processor interactively selecting a point of view in response to inputs from the user input device;

    a coprocessor coupled to the main processor, the coprocessor providing a predetermined graphics feature set for interactively generating image data in response to the selected point of view by projecting polygons representing a three dimensional world onto a two dimensional viewing plane, the coprocessor including;

    a signal processor that is shared between at least graphics functions and audio processing functions, the signal processor including a scalar unit and a vector unit, the vector unit capable of performing plural calculations in parallel, the signal processor including a microcode store that stores microcode, the signal processor executing the microcode in the microcode store to perform the graphics and audio processing functions;

    a display processor comprising display pipeline hardware that alternatively provides a one-pixel-per-cycle mode and a two-pixel-per-cycle mode to minimize hardware while providing a rich feature set including level-of-detail processing, the display pipeline hardware including a texture memory having first and second parts, the texture memory first part being capable of storing texture maps that are color indexed and texture maps that are not color indexed, the texture memory second part being capable of storing texture maps and/or color lookup tables for the color indexed texture maps, a video interface, an audio interface, a serial interface, and a parallel peripheral interface, wherein each of the signal processor, the display processor, the video interface, the audio interface, the serial interface and the parallel peripheral interface includes circuitry for accessing a main memory;

    the main memory being coupled to the coprocessor via a 9 bit wide bus, the main memory providing a common address space for the coprocessor and the main processor, the main memory storing at least the following data structures;

    instructions for execution by the main processor;

    a color frame buffer;

    a depth buffer;

    graphics microcode;

    audio processing microcode;

    at least one display list;

    at least one texture map; and

    at least one audio output buffer;

    a video signal generating circuit coupled to the coprocessor video interface, the video signal generating circuit generating a video signal for display on a color television set;

    a removable storage device including a housing, a security chip, a read only memory and at least one further memory device, the coprocessor including an arrangement that maps the read only memory and the further memory device into the main processor address space, the read only memory initially storing the graphics and audio processing microcode; and

    a connector that connects the coprocessor to the removable storage device; and

    a serial peripheral interface circuit coupled to the coprocessor serial interface, the serial peripheral interface circuit including a processor that performs serial interface functions and security functions and further includes a boot ROM that provides main processor initial program load instructions, the serial interface circuit processor being coupled to the removable storage device security chip through the connector.

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