Allocation for back-to-back misses in a directory based cache

• US 6,332,179 B1
• Filed: 08/19/1999
• Issued: 12/18/2001
• Est. Priority Date: 08/19/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation, Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: International Business Machines Corporation
• Inventors: Hardage, James N. Jr., Okpisz, Alexander E.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US09/377,636
• Time in Patent Office: 852 Days
• Field of Search: 711/128, 711/140
• US Class Current: 711/140
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing

Abstract

A preferred embodiment of the present invention includes a memory caching system that uses a method for allocating blocks of memory by: determining if the contents at a selected memory address are stored in the cache by comparing the selected memory address to the addresses stored in the directory, if the selected memory address is not in the cache, allocating a place in the directory for selected address, wherein, if a place in the directory for an address having the same cache line as the selected memory address is in the process of allocating or has been previously allocated, the selected memory address is allocated to that location of the pending or previous allocation.

Claims

1. A memory system including a cache memory comprising:

a plurality of memory blocks, each memory block being associated with a tag stored in a directory; and

a controller for determining if the contents at a selected memory address are stored in the cache by comparing the selected memory address to the addresses stored in the directory, if the selected memory address is not in the cache, allocating a place in the directory for selected address, wherein, if a place in the directory for an address having the same cache line as the selected memory address is in the process of allocation or has been previously allocated, the selected memory address is allocated to that location of the pending allocation or previously allocated place in the directory.

2. A memory system as in claim 1 wherein the memory system provides data storage and retrieval for a multiprocessor system.

3. A memory system as in claim 1 wherein the cache memory is a static random access memory.

4. A memory system as in claim 1 wherein the data assigned to each tag is divided into sectors containing 32 bytes of data.

5. A memory system as in claim 1 wherein the cache memory is one of a plurality of cache memories, each of the plurality of cache memories providing a different cache level.

6. A memory system as in claim 1 wherein the blocks of memory of the cache memory are addressed using a fully associative addressing scheme.

7. A memory system as in claim 1 wherein the blocks of memory of the cache memory are addressed using a set associative addressing scheme.

8. A processing system comprising:

at least one processor;

a system memory; and

a cache memory that caches data stored in the system memory for delivery to the processor in response to access commands from the processor, comprising;

a plurality of memory blocks, each memory block being associated with a tag; and

a controller for determining if the contents at a selected memory address are stored in the cache by comparing the selected memory address to the addresses stored in the directory, if the selected memory address is not in the cache, allocating a place in the directory for selected address, wherein, if a place in the directory for an address having the same cache line as the selected memory address is in the process of allocation or has been previously allocated, the selected memory address is allocated to that location of the pending allocation or previously allocated place in the directory.

9. A processing system as in claim 8 wherein the at least one processor comprises a plurality of processors.

10. A processing system as in claim 8 wherein the cache memory is a static random access memory.

11. A processing system as in claim 8 wherein the data assigned to each tag is divided into sectors containing 32 bytes of data.

12. A processing system as in claim 8 wherein the cache memory is one of a plurality of cache memories, each of the plurality of cache memories providing a different cache level.

13. A processing system as in claim 8 wherein the blocks of memory of the cache memory are addressed using a fully associative addressing scheme.

14. A processing system as in claim 8 wherein the blocks of memory of the cache memory are addressed using a set associative addressing scheme.

15. A method for allocating blocks of memory in a cache memory, comprising the steps of:

determining if the contents at a selected memory address are stored in the cache by comparing the selected memory address to the addresses stored in the directory;

if the selected memory address is not in the cache, allocating a place in the directory for selected memory address, wherein, if a place in the directory for an address having the same cache line as the selected memory address is in the process of allocation or has been previously allocated, the selected memory address is allocated to that location of the pending allocation or previously allocated place in the directory.

16. A method as in claim 15 wherein the cache memory is included in a memory system that provides data storage and retrieval for a multiprocessor system.

17. A method as in claim 15 wherein the cache memory is a static random access memory.

18. A method as in claim 15 wherein the data assigned to each tag is divided into sectors containing 32 bytes of data.

19. A method as in claim 15 wherein the cache memory is one of a plurality of cache memories, each of the plurality of cache memories providing a different cache level.

20. A method as in claim 15 wherein the blocks of memory of the cache memory are addressed using a fully associative addressing scheme.

21. A method as in claim 15 wherein the blocks of memory of the cache memory are addressed using a set associative addressing scheme.

22. A method for data processing comprising the steps of:

providing at least one processor;

providing a system memory; and

providing a cache memory that caches data stored in the system memory for delivery to the processor in response to access commands from the processor, the cache memory including a plurality of memory blocks, each memory block being associated with a tag;

determining if the contents at a selected memory address are stored in the cache by comparing the selected memory address to the addresses stored in the directory;

if the selected memory address is not in the cache, allocating a place in the directory for selected memory selected address, wherein, if a place in the directory for an address having the same cache line as the selected memory address is in the process of allocation or has been previously allocated, the selected memory address is allocated to that location of the pending allocation or previously allocated place in the directory.

23. A method as in claim 22 wherein the at least one processor comprises a plurality of processors.

24. A method as in claim 22 wherein the cache memory is a static random access memory.

25. A method as in claim 22 wherein the data assigned to each tag is divided into sectors containing 32 bytes of data.

26. A method as in claim 22 wherein the cache memory is one of a plurality of cache memories, each of the plurality of cache memories providing a different cache level.

27. A method as in claim 22 wherein the blocks of memory of the cache memory are addressed using a fully associative addressing scheme.

28. A method as in claim 22 wherein the blocks of memory of the cache memory are addressed using a set associative addressing scheme.