Method of forming gate electrode in semiconductor device

• US 6,333,250 B1
• Filed: 12/14/1999
• Issued: 12/25/2001
• Est. Priority Date: 12/28/1998
• Status: Expired due to Fees

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Hyeon Soo
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US09/460,557
• Time in Patent Office: 742 Days
• Field of Search: 438/585, 438/592, 438/595, 438/593, 438/594
• US Class Current: 438/595
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon

Abstract

A method of forming a gate electrode in a semiconductor device is disclosed. A method of forming a gate electrode in a semiconductor device according to the present invention includes steps of: forming a gate oxide layer, a polysilicon layer, a diffusion barrier layer, a metal layer and a mask layer on a semiconductor substrate, in sequence; patterning the mask layer, the metal layer and the diffusion barrier layer to the first width; patterning the mask layer, the metal layer and the diffusion barrier layer having the first width to a second width by wet etching; forming a spacer on the side walls of the mask layer, the metal layer and the diffusion barrier layer having the second width; and patterning the polysilicon layer and the gate oxide layer using the mask layer and the spacer as an etch barrier.

Claims

1. A method of forming a gate electrode in a semiconductor device, comprising the steps of:

forming a gate oxide layer, a polysilicon layer, a diffusion barrier layer, a metal layer and a mask layer on a semiconductor substrate, in sequence;

patterning the mask layer, the metal layer and the diffusion barrier layer to the first width;

patterning the mask layer, the metal layer and the diffusion barrier layer having the first width to a second width by wet etching;

forming a spacer on the side walls of the mask layer, the metal layer and the diffusion barrier layer having the second width; and

patterning the polysilicon layer and the gate oxide layer using the mask layer and the spacer as an etch barrier.

2. The method according to claim 1, wherein the gate oxide layer is formed to the thickness of 50 to 100 Å

.

3. The method according to claim 1, wherein the polysilicon layer is formed to the thickness of 500 to 1,000 Å

.

4. The method according to claim 1, wherein the diffusion barrier layer is formed of a nitride layer such as a titanium nitride(TiN) layer or a tungsten nitride(WN) layer.

5. The method according to claim 1, wherein the diffusion barrier layer is formed to the thickness of 10 to 500 Å

.

6. The method according to claim 4, wherein the diffusion barrier layer is formed to the thickness of 10 to 500 Å

.

7. The method according to claim 1, wherein the metal layer is formed of a tungsten layer.

8. The method according to claim 7, wherein the tungsten layer is formed to the thickness of 100 to 2,000 Å

.

9. The method according to claim 1, wherein the mask layer is formed of one selected from the group consisting of an oxide layer, a nitride layer and a stacked layer of the oxide layer and the nitride layer.

10. The method according to claim 1, wherein the mask layer is formed to the thickness of 1,000 to 2,000 Å

.

11. The method according to claim 9, wherein the mask layer is formed to the thickness of 1,000 to 2,000 Å

.

12. The method according to claim 1, wherein the wet etching is performed using etchant wherein etching selectivity of the mask layer, the tungsten layer and the diffusion barrier layer are equalized to each other, and etching selectivity of the mask layer, the tungsten layer and the diffusion barrier layer to the polysilicon layer is over 20:

1.

13. The method according to claim 1, wherein the wet etching is performed so that the first width of the mask layer, the metal layer and the diffusion barrier layer are etched as 50 to 500 Å

.

14. The method according to claim 1, wherein the spacer is formed of one selected from the group consisting of an oxide layer, a nitride layer and a stacked layer of the oxide layer and the nitride layer.

15. The method according to claim 1, wherein the width of the spacer is 50 to 500 Å

.

16. The method according to claim 14, wherein the width of the spacer is 50 to 500 Å

.